Quartus warning

I was trying to use the SDRAM controller
without using the NIOS. I am now using the vhdl file generated from
SOPC builder.

Things are great during simulation i.e. However, when I try to
synthesize it. I receive the following warning message:

Warning: Can't pack node sdram_0:sdram_con_inst|m_addr[10] to I/O pin.
+Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and
I/O node zs_addr[10] -- logic cell cannot be packed as I/O register
+Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and
I/O node sdram_0:sdram_con_inst|m_addr[10] -- logic cell cannot be
packed as I/O register
+Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and
I/O node sdram_0:sdram_con_inst|i~28445 -- logic cell cannot be packed
as I/O register

The m_addr[10] ties to the address pin of the RAM. Bits 9 and 8 are
the same as well. Can't seem to find out the reason.

I understand that a register is inserted at the pins to optimize
timing. If this this node is not packed, does it mean to say that it
is bypassed to the pin. In a sentence, how does this impact
functionality?

Timing analyzer tests indicate that +ve slack so in the end, timing
seems up to scratch.

Thanks for your help! ;->
Ted

ted644@hotmail.com (Ted) wrote in message news:<cd8a739a.0408120853.6a3147a8@posting.google.com>...
> I was trying to use the SDRAM controller
> without using the NIOS. I am now using the vhdl file generated from
> SOPC builder.
> 
> Things are great during simulation i.e. However, when I try to
> synthesize it. I receive the following warning message:
> 
> Warning: Can't pack node sdram_0:sdram_con_inst|m_addr[10] to I/O pin.
> +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and
> I/O node zs_addr[10] -- logic cell cannot be packed as I/O register
> +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and
> I/O node sdram_0:sdram_con_inst|m_addr[10] -- logic cell cannot be
> packed as I/O register
> +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and
> I/O node sdram_0:sdram_con_inst|i~28445 -- logic cell cannot be packed
> as I/O register
> 
> The m_addr[10] ties to the address pin of the RAM. Bits 9 and 8 are
> the same as well. Can't seem to find out the reason.
> 
> I understand that a register is inserted at the pins to optimize
> timing. If this this node is not packed, does it mean to say that it
> is bypassed to the pin. In a sentence, how does this impact
> functionality?
> 
> Timing analyzer tests indicate that +ve slack so in the end, timing
> seems up to scratch.

Ted,

Warnings like this normally come from the fitter, and indicate that an
assignment (generally a FAST_INPUT_REGISTER or FAST_OUTPUT_REGISTER
assignment) that requested that a register be placed in an IO cell
could not be honoured.

You should check the sub-messages around this message (by clicking on
the "+" to expand the sub-messages, if you're running in the GUI) and
right click on the messages to get on-line help on why the register
couldn't go in the IO cell.

If you met all your timing constraints anyway, the design will still
work fine.  Putting the registers in the IO cell is purely a
performance optimization to improve IO timing.  You should make sure
that the timing constraints are complete though (i.e. you have timing
constraints on everything you care about), since the timing analyzer
only analyzes what you ask it to.

Vaughn
Altera