Xilinx Spartan3 DCM Procedure

Not sure what to do here.  I ran the wizard for a Single DCM which generated
a XAW file.  Although this is a "New Source" it doesn't act like one. One
can generate VHDL code from this XAW file which I did.  I then tried to add
the VHDL code as a source and got an error message.  Something about a
conflict between the two files.  So I deleted the XAW file and now the VHDL
file, by itself, seems to work, that is, it will synthesize and download.  I
haven't been able to verify the clock outputs yet. Is the XAW file suppose
to be part of the project source?

Hi,

The vhdl file is just a wrapper file, so your DCM hasn't been implemented. You
have to attach the XAW file to your project. Coregen or the architecture wizard
give you a netlist and not an open VHDL source code most of the time.

Vincent.

Brad Smallridge wrote:

> Not sure what to do here.  I ran the wizard for a Single DCM which generated
> a XAW file.  Although this is a "New Source" it doesn't act like one. One
> can generate VHDL code from this XAW file which I did.  I then tried to add
> the VHDL code as a source and got an error message.  Something about a
> conflict between the two files.  So I deleted the XAW file and now the VHDL
> file, by itself, seems to work, that is, it will synthesize and download.  I
> haven't been able to verify the clock outputs yet. Is the XAW file suppose
> to be part of the project source?