Dear all, I am very new in vhdl, can anybody tell me what problem, following is code : disp_ena : OUT STD_LOGIC; --) column : OUT INTEGER; -- row : OUT INTEGER;: .......................................... --set pixel coordinates IF(h_count < h_pixels) THEN --horiztonal display time column <= h_count; --set horiztonal pixel coordinate END IF; IF(v_count < v_pixels) THEN --vertical display time row <= v_count; --set vertical pixel coordinate END IF; --set display enable output IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time disp_ena <= '1'; --enable display ELSE --blanking time disp_ena <= '0'; --disable display END IF; AND it has following ERROR ERROR:HDLParsers:409 - "D:/xil_add/1/eewiki_vga/vga_controller.vhd" Line 67. Signal 'column' column is at left hand side of variable assignment statement. ERROR:HDLParsers:409 - "D:/xil_add/1/eewiki_vga/vga_controller.vhd" Line 68. Signal 'row' row is at left hand side of variable assignment statement.
ERROR:HDLParsers:409 .... at left hand side. Please help
Started by ●November 19, 2015
Reply by ●November 19, 20152015-11-19
On 2015-11-19 16:24:00 +0000, abirov@gmail.com said:> Dear all, I am very new in vhdl, can anybody tell me what problem, > following is code : > disp_ena : OUT STD_LOGIC; --) > column : OUT INTEGER; -- > row : OUT INTEGER;: > .......................................... > --set pixel coordinates > IF(h_count < h_pixels) THEN --horiztonal display time > column <= h_count; --set horiztonal pixel coordinate > END IF; > > IF(v_count < v_pixels) THEN --vertical display time > row <= v_count; --set vertical pixel coordinate > END IF; > > --set display enable output > IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time > disp_ena <= '1'; --enable display > ELSE --blanking time > disp_ena <= '0'; --disable display > END IF; > AND it has following ERROR > > ERROR:HDLParsers:409 - "D:/xil_add/1/eewiki_vga/vga_controller.vhd" > Line 67. Signal 'column' column is at left hand side of variable > assignment statement. > ERROR:HDLParsers:409 - "D:/xil_add/1/eewiki_vga/vga_controller.vhd" > Line 68. Signal 'row' row is at left hand side of variable assignment > statement.You didn't provide line numbers with your listing but look at the third line closely and you will see what might be causing the problem.
Reply by ●November 20, 20152015-11-20
Am Donnerstag, 19. November 2015 17:24:13 UTC+1 schrieb abi...@gmail.com:> Dear all, I am very new in vhdl, can anybody tell me what problem, > following is code : > disp_ena : OUT STD_LOGIC; --) > column : OUT INTEGER; -- > row : OUT INTEGER;:> ERROR:HDLParsers:409 - "D:/xil_add/1/eewiki_vga/vga_controller.vhd" Line 67. Signal 'column' column is at left hand side of variable assignment statement. > ERROR:HDLParsers:409 - "D:/xil_add/1/eewiki_vga/vga_controller.vhd" Line 68. Signal 'row' row is at left hand side of variable assignment statement.You did not provide the relevant part of code. "column" and "row" are outputs and therefore signals, the errormessage indicates you use them in variable assignment (row := ABC) instead of signal assignments (row <= ABC) in line 67 and 68. regards, Thomas
Reply by ●November 23, 20152015-11-23
Here is my code,here is no errors and warnings, but even no warnings and no errors (i think adv7125 problem) it doesnot work.I have old ML405 board and it use ADV7125,and monitor is Acer AL1511 used 1024X768,I use LED out for checking whether is reset works or not, and also checked for CLK (LED <= clk65MHZ)so thats ok, Here is all code: (vga.vhd) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.Numeric_STD.All; entity VGA is port ( clk100MHz : in std_logic; reset_n : in std_logic; HSYNC : out std_logic; VSYNC : out std_logic; VGA_R,VGA_G,VGA_B: out std_logic_vector(3 downto 0); VGA_CLK : out std_logic; LED : out std_logic ); end VGA; architecture main of vga is signal clk65MHz: std_logic:='0'; ------------------------------------------------------------- component clock port ( clk100MHz: in std_logic; clk65MHz: out std_logic ); end component; ------------------------------------------------------------- component SYNC port ( clk65MHz : in STD_LOGIC; reset_n: in STD_LOGIC; HSYNC,VSYNC : OUT STD_LOGIC; --LEDo,LED1o : OUT STD_LOGIC; VGA_R,VGA_G,VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0) ); end component; --------------------------------------------------------------- begin C1: SYNC port map (clk65MHz,reset_n, HSYNC, VSYNC, VGA_R => VGA_R, VGA_G => VGA_G, VGA_B => VGA_B ); C2 : clock port map (clk100MHz,clk65MHz); LED <= reset_n; VGA_CLK <= clk65MHz; end main; (*.vhd) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity SYNC is PORT( reset_n: in STD_LOGIC; clk65MHz: in STD_LOGIC; HSYNC,VSYNC : OUT STD_LOGIC; VGA_R,VGA_G,VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0) ); end SYNC; architecture main of SYNC is SIGNAL HPOS: INTEGER RANGE 0 TO 1344:=0; --1688:=0; SIGNAL VPOS: INTEGER RANGE 0 TO 806:=0; --1066:=0; begin process (clk65MHz,reset_n) begin IF rising_edge(clk65MHz) and reset_n = '1' then if HPOS=740 or VPOS=554 then VGA_R<=(OTHERS=>'1'); VGA_G<=(OTHERS=>'1'); VGA_B<=(OTHERS=>'1'); else VGA_R<=(OTHERS=>'0'); VGA_G<=(OTHERS=>'0'); VGA_B<=(OTHERS=>'0'); end if; if HPOS<1344 then HPOS<=HPOS+1; else HPOS<=0; if VPOS<806 then VPOS<=VPOS+1; else VPOS<=0; end if; end if; if HPOS>24 and HPOS<160 then HSYNC<='0'; else HSYNC<='1'; end if; if VPOS>3 and VPOS<9 then VSYNC<='0'; else VSYNC<='1'; end if; if ((HPOS>0 and HPOS<320)or(VPOS>0 and VPOS<38))then VGA_R<=(others=>'0'); VGA_G<=(others=>'0'); VGA_B<=(others=>'0'); end if; end if; end process; end main; clock.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clock is port ( clk100MHz: in std_logic; clk65MHz: out std_logic ); end clock; architecture Behavioral of clock is signal Counter: std_logic_vector(25 downto 0); signal CLK_1Hz: std_logic; begin Prescaler: process(clk100MHz) begin if rising_edge(clk100MHz) then if Counter < "10111110101111000010000000" then Counter <= Counter + 64999999; else CLK_1Hz <= not CLK_1Hz; Counter <= (others => '0'); end if; end if; end process prescaler; clk65MHz <= CLK_1Hz; end Behavioral;
Reply by ●November 23, 20152015-11-23
my UCF file, NET "clk100MHz" LOC = "AB14"; --clock from ML405 clock generator NET "VGA_CLK" LOC = "AC7"; --clock to ADV7125 NET "reset_n" LOC = "d6"; NET "LED" LOC = "A10"; #NET "LED1" LOC = "B10"; #NET "LED2" LOC = "F13"; ####################### VGA ###################### NET "VGA_B<0>" LOC = "f4" ; NET "VGA_B<1>" LOC = "j4" ; NET "VGA_B<2>" LOC = "g9" ; NET "VGA_B<3>" LOC = "j5" ; #NET "VGA_B<4>" LOC = "h3" ; NET "VGA_G<0>" LOC = "j3" ; NET "VGA_G<1>" LOC = "k7" ; NET "VGA_G<2>" LOC = "k3" ; NET "VGA_G<3>" LOC = "g10" ; #NET "VGA_G<4>" LOC = "k6" ; NET "VGA_R<0>" LOC = "f3" ; NET "VGA_R<1>" LOC = "h7" ; NET "VGA_R<2>" LOC = "e3" ; NET "VGA_R<3>" LOC = "g5" ; #NET "VGA_R<4>" LOC = "d3" ; ##################### SYNCs ######################## NET "HSYNC" LOC = "C3" ; NET "VSYNC" LOC = "D4" ;
Reply by ●November 24, 20152015-11-24
I had a look at the datasheet at http://web.mit.edu/6.111/www/f2009/handouts/labs/ADV7125.pdf Maybe you also need to drive the "blank" pin, or the "psave".... It would pay to check the schematic...
Reply by ●December 27, 20152015-12-27
On Wednesday, November 25, 2015 at 2:29:15 AM UTC+6, Mike Field wrote:> I had a look at the datasheet at http://web.mit.edu/6.111/www/f2009/handouts/labs/ADV7125.pdf > > Maybe you also need to drive the "blank" pin, or the "psave".... > > It would pay to check the schematic...Hello , thank you for your answer. I generate psave,nsync,nblank and 5 common signals and it starts to work normal, thank you everyone !!!