Configuration : Virtex-E, CLB column

Dear all, <br><br>Subject: Virtex-E, CLB column. <br><br>Inside a Xilinx Virtex-E FPGA, 5 types of column are present (Centre, CLB, Block SelectRAM Interconnect, Block SelectRAM Content, Right-Left IOB Columns). Let's take in account the CLB column. Each CLB column contains 2 Top IOB blocks, 2 Bottom IOB blocks and a certain number of "CLB" blocks. Each "CLB" block contains the information about the CLB by itself (Configuration), the routing (SB and CB). <br><br>Firstly, is it correct. And secondly, how are organized these information in a frame or better in a "CLB" block. <br><br>Best regards, <br>
/Cyrille Lambert