Questions about clocks on the Cyclone Nios development board

I have a Cyclone Nios development board, which I'm using for some test
development work.  The clocking system on the board seems very strange to
me - I'm wondering if it *is* strange, or if I've just misunderstood things.
The board has a 50 MHz oscillator that is used to generate the base clock
for the fpga and a signal out to the prototyping cards.  That's fair enough.
However, there is only one available clock signal out of the fpga, which is
then passed through an external clock buffer to generate clocks to the
prototype cards and a feedback signal to the fpga.  I find this painfully
limiting, and can't think of a good reason why the card is designed this
way.  It means I have to use the same clock signal to both prototype
connectors, and it means that the feedback signal used for the sdram pll
comes from this same clock.  In my design, I want the processor to run at 60
MHz, while the external clock to the prototype cards is at 50 MHz.  This
means that the sdram pll must generate its 60 Mhz signal from a 50 MHz
feedback, independantly from the main 60 MHz system clock.  The phases for
these clocks are therefore not determined - sometimes my sdram works,
sometimes not.  Is there something I'm missing here, or is it just a strange
card design?

--
David

"I love deadlines.  I love the whooshing noise they make as they go past."
Douglas Adams