Isn't this a rather clumsy piece of code? Isn't there a way to use a few simple lines to infer a block ram (that is not written) and then init the contents separately? It is not often that I want to hard code my ROM contents. Subroto Datta wrote:> > Hello Sebastian, > You have a pointed out an error in the handbook which will be > corrected. The piece of code that will infer a ROM in Quartus (used > 4.1) is shown below: > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > ENTITY sync_rom IS > PORT ( > clock: IN STD-LOGIC; > address: IN STD_LOGIC_VECTOR(7 downto 0); > data_out: OUT STD_LOGIC_VECTOR(5 downto 0) > ); > END sync_rom; > > > > ARCHITECTURE rtl OF sync_rom IS > BEGIN > PROCESS (clock) > BEGIN > IF rising_edge(clock) THEN > CASE address IS > WHEN "00000000" => data_out <= "101111"; > WHEN "00000001" => data_out <= "110110"; > ... > > WHEN "11111110" => data_out <= "000001"; > WHEN "11111111" => data_out <= "101010"; > WHEN OTHERS => data_out <= "101111"; > END CASE; > END IF; > END PROCESS; > > END rtl; > > > Hope this helps, > > Subroto Datta > Altera Corp.-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
altera quartus II handbook is wrong??
Started by ●September 15, 2004
Reply by ●September 27, 20042004-09-27
Reply by ●September 27, 20042004-09-27
glen herrmannsfeldt wrote:> > rickman wrote: > (snip about ROMs in FPGA's) > > > I'm not sure I follow this, but in an FPGA a ROM is nothing but a RAM > > that is never written. You can infer them the same way as a RAM, just > > don't use a write signal and input data. They can be initialized in > > different ways. I find it most useful to init the data *after* > > compliation and routing of the design. Both Xilinx and Altera support > > this. > > Quartus II for me, if I have a design with RAM in it, such > as a FIFO has a warning that I haven't provided initialization > data for the RAM. I believe it takes the old intel hex format, > and maybe others. > > Are you using the BRAM's or LUT's for your ROM?I am talking about block rams. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●October 1, 20042004-10-01
rickman <spamgoeshere4@yahoo.com> wrote in message news:<41583A6C.827D2CFF@yahoo.com>...> Isn't this a rather clumsy piece of code? Isn't there a way to use a > few simple lines to infer a block ram (that is not written) and then > init the contents separately? It is not often that I want to hard code > my ROM contents. > > >I was adhering to the customer's code sample when formulating the original reply reply. To achieve what you want you can do the following: The easiest way to make a ROM that can be initialized separately is to instantiate an Altera megafunction. You can use the MegaWizard Plug-In Manager (Tools menu) to configure the block and look at a specific initialization file and then you can change the contents of the file later on. The LPM_ROM is a part of the LPM standard and and shoud be supported by most FPGA CAD tools. - Subroto Datta Altera Corp.
Reply by ●October 15, 20042004-10-15
Subroto Datta wrote:> > rickman <spamgoeshere4@yahoo.com> wrote in message news:<41583A6C.827D2CFF@yahoo.com>... > > Isn't this a rather clumsy piece of code? Isn't there a way to use a > > few simple lines to infer a block ram (that is not written) and then > > init the contents separately? It is not often that I want to hard code > > my ROM contents. > > > > > > > > I was adhering to the customer's code sample when formulating the > original reply reply. To achieve what you want you can do the > following: > > The easiest way to make a ROM that can be initialized separately is to > instantiate an Altera megafunction. You can use the MegaWizard > Plug-In Manager (Tools menu) to configure the block and look at a > specific initialization file and then you can change the contents of > the file later on. > > The LPM_ROM is a part of the LPM standard and and shoud be supported > by most FPGA CAD tools.Thanks for the reply. I guess I missed it until now. "Easiest" is a subjective term. I avoid all instantiations if I can to make the code more portable. Is there a way to use an initialization file with inferred RAM or ROM? In my case it actually will be RAM since the processor can update its own program. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●October 15, 20042004-10-15
rickman <spamgoeshere4@yahoo.com> wrote in message news:<416F5B46.94C42BCB@yahoo.com>...> "Easiest" is a subjective term. I avoid all instantiations if I can to > make the code more portable. Is there a way to use an initialization > file with inferred RAM or ROM? In my case it actually will be RAM since > the processor can update its own program. >Hi Rick, We hear you and are working on specifying the initialization file within the HDL. It will be available in one of the 2005 releases. Hope this helps, Subroto Datta Altera Corp.
