Four_Bit_Counter in VHDL

 I am implementing four-bit-counter but I am getting value of x for Port_co=
unter in auto-counting. http://pastebin.com/z1Kh7D3J (VHDL code) and http:/=
/pastebin.com/2kY3hQAN (testbench). I already finished the two flip-flop in=
 VHDL. I am now stuck with simulation. http://i.imgur.com/WXFQC5f.png

 Someone told me that the usual reason for an undefined output is failure t=
o initialize all signal. So, I uncommented the clock_enable process and  ch=
ange the VHDL source to http://pastebin.com/y0j5iBBL ,but simulation just w=
on't stop. Did I code my clock_enable process correctly?

even after I manually stop the simulation, the waveform window is EMPTY

Any help ?