add/sub 2:1 mux and ena in a single LE (Cyclone)

Hi Martin,

> However, if the LAB global inputs such as 'sload' and 'ena' are not
available
> for the synthesizer you're 'wasting' resources. Do you use these signals
for other
> functions (perhaps the loadable counter)?

This problem is specific to combining the addsub feature with the sload
signal (I think).  When you write a vanilla loadable counter or other such
code that requires an sload, enable, etc. Quartus should be using the LE
properly.

Note: There are some circumstances where we do not use an sload or other
control signal even though we could.  For example, I don't think we
recommned that synthesis tools use sload or enable as general logic signals
since these signals are shared LAB wide and if you and up with oodles of
independent sload or enable signals in a design, there will be poor packing.
That's an example where even though the synthesis will use fewer LEs, the #
of LABs required will be higher and thus the synthesis is "larger".

> BTW.: Do we really need asynchronous signals such as PRN/ALD, ADATA
> and CLRN (ok this one for the asynch. reset) in these days? Isn't that a
waste
> of resources usfull only for a some designed who doing asynchronous
design.

The quick answer is no, no one should be using many asynchronous control
signals.  But users do, and if the user writes their (bad?) HDL so that they
have async signals, and we don't have the hardware, our only choice is to
emulate the async functionality using logic elements.  And then you get into
some difficulty with the start-up condition of these soft flip-flops,
potential glitch issues if not careful, etc.

If you look carefully at Cyclone II, we have removed the aload capability
since this is cheaper to implement in soft logic for those few times people
use it -- we might as well tax the users with aloads rather than burden
every user with the slight silicon bloat there would be with hard support.

> > In the meantime, there is a work-around.  You can directly instantiate
> > "stratix_lcells" (the WYSIWYG cell for Stratix/Cyclone LEs).  Below I
give
>
> Is there some documentation about these AYSIAYG lcells? I was looking for
such
> an entity in the Megafunctions/LPM help of Quartus (befor you provided the
solution)
> to implement this function. However, I did not find these basic
megafunction.

There is no "user" documentation on the WYSIWYG (I like the all version
;-)).  We are working on some documentation that may be released in the
future.  In the meantime, you can also download the QUIP toolkit (search for
QUIP on www.altera.com).  This is a package we make available for academics
who are designing CAD tools.  It provides a document describing the Stratix
(and thus Cyclone and Max II) LE WYSIWYGs.

Regards,

Paul Leventis
Altera Corp.

Jan Gray wrote:
> In Virtex-derived architectures, you can implement
>  o = add ? (a + b) : c;
> or
>  o = sel ? (a + b) : (a + c);
> or even
>  o = addsub ? (addand ? a+b : a-b) : (addand ? a&b : a^b);
> in one LUT per bit.
> 
> The trick is to use a MULT_AND to kill the carry propagation when add=0.
> See http://www.fpgacpu.org/log/nov00.html#001112.
> 
> But as Philip points out, you'd need five input signals to do
>   o = sel ? (add ? a + b : a - b) : c;
> and I don't think that can be done in one LUT per bit.

After rechecking more closely, I better understand.

More generaly :

	o = addsub ? (add_aux ? a+b : a-b) : ( F(a,b,add_aux) )

with F(a,b,add_aux) any function ...


Solutions would be to either not load from a third bus but implement a
load operand A or load operand B (even both, selecting which to load
via add_aux).

Also, depending on where the the load operand comes : If it comes from
a mux and that mux has a 'spare' input, connect that spare input to
every time the add or sub selector. Then send the load via add_aux signals. When add_sub is
used, on your mux, use the add or sub signal.



Sylvain