How many Altera LE's to Xilinx Slices????

The answare is

      1 slice into a Spartan 3
    16 LE   into a MAX-II

Can you compare this architectures as  1 Slice = 2 LE's  ?

Walter.


"Walter Gallegos" <walter@chasque.apc.org> a &#4294967295;crit dans le message de
news:10n13v2dqalbv6a@news.supernews.com...
>
> "Guitarman" <ericjohnholland@hotmail.com> a &#4294967295;crit dans le message de
> news:90282e35.0410151112.77a87654@posting.google.com...
> > Hello All,
> >
> > I've been designing with Xilinx FPGAs for a while so I'm used to the
> > "Slice" concept. I'm looking at Altera's Max II as a nice possible
> > solution for a design.
> >
> > I took my VHDL code and it synthesized to 40 Slices in a Spartan III.
> > Then I took the same code and sythesized it for a Max II (using
> > Quartus II now) and it was 71 LE's.
> >
> > I realize a blanket statement 71 LE's (approx. =) 40 Slices, is totaly
> > dependant on how the code is sysnthesized.
> >
> > But is a approximate 1 Slice = 2 LE's a pretty close all around
> > estimate.
> >
> > Thanks
> > Eric
>
> I disagree,  both architectures are different, you can't compare it in
this
> way
> have how many slices into the following code ?
> .....
>         DI : in std_logic;
>         DO : out std_logic;
>         CLOCK : in std_logic;
> .....
> .......
>    signal temp: std_logic_vector(15 downto 0);
> ......
> begin
>
>    Demo : process(CLOCK)
>    begin
>       if rising_edge(CLOCK) then
>          temp<= temp(14 downto 0) & DI;
>       end if;
>    end process Demo;
>
>    DO <= temp(15);
> ....
>
>
>
>

"Walter Gallegos" <walter@chasque.apc.org> wrote in message 
news:10n2h60q87tig87@news.supernews.com...
> The answare is
>
>      1 slice into a Spartan 3
>    16 LE   into a MAX-II
>
> Can you compare this architectures as  1 Slice = 2 LE's  ?
>

I agree that there some areas that you can't simply compare the two 
architectures. For example, I had an old design with an Altera 10K series 
that used a fully async RAM block. Now, move it to a Spartan 3 architecture 
and you see that you should use the whole chip just to make that block of 
async RAM!
However, it is perfectly understandable that a user might need to compare 
different available options and to do this, he/she would need to have rough 
estimates to compare a Xilinx device to that of Altera. For example, 
recently I had this interesting offer for a an FPGA prototype  board with 
the same price of $99 for an Altern EP1C12 or a Xilinx XC3S400. I would like 
to use a prototype board for very different designs so I had to compare 
between the two chips. As I program in VHDL and use synthesize tools, I 
don't really care for any specific architecture (unless something like your 
example or my example above happens) and the thing that matters in cases 
like that is you only look for the BIGGER FPGA. To do it, you need to 
compare and to compare you can only use rough estimates.
Personally, I find the simple equation of 1 Slice = 2 LE a very good rough 
estimate and for many designs it gives you a good answer. You have a very 
specific design and need a very good answer? Fire your synthesize tool and 
see how much resources you'd really need! 

Depends heavily on the design.  Xilinx packs tighter for certain
arithmetic because of the structure of the LUT and carry chain: Altera's
carry chain through stratix breaks the 4 lut into a pair of 3 LUTs, one
for sum one for carry so it limits the number of inputs per bit.  Stratix
adds a little bit of extra logic to the LE to allow implementation of an
adder subtractor without going to two levels of logic, and there is a way
to load data bypassing the adder which provides single level solutions for
those specific (and fairly common) cases.  Xilinx will also allow you to
turn the LE into a 16 element shift register, which can be very handy not
only for shift register delays, but also for reloadable LUTs, which are
useful for things like adaptive DA filters.  Altera has more options for
the memory structure, which in many cases makes it more efficient for
certain types of designs requiring memory.  My point is both vendor's
offerings have some strong points, and which one is best depends heavily
on your application.

Guitarman wrote:

> Hello All,
>
> I've been designing with Xilinx FPGAs for a while so I'm used to the
> "Slice" concept. I'm looking at Altera's Max II as a nice possible
> solution for a design.
>
> I took my VHDL code and it synthesized to 40 Slices in a Spartan III.
> Then I took the same code and sythesized it for a Max II (using
> Quartus II now) and it was 71 LE's.
>
> I realize a blanket statement 71 LE's (approx. =) 40 Slices, is totaly
> dependant on how the code is sysnthesized.
>
> But is a approximate 1 Slice = 2 LE's a pretty close all around
> estimate.
>
> Thanks
> Eric

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Ray Andraka wrote:

> Depends heavily on the design.  Xilinx packs tighter for certain
> arithmetic because of the structure of the LUT and carry chain: Altera's
> carry chain through stratix breaks the 4 lut into a pair of 3 LUTs, one
> for sum one for carry so it limits the number of inputs per bit.  

(snip)

I still miss the XC4000 series where the carry chain was separate
from the LUTs, for convenient implementation of saturating adders
and MAX(a,b) functions by feeding the carry out or overflow
back to an LUT input.

-- glen

Yeah, me too.

glen herrmannsfeldt wrote:

> Ray Andraka wrote:
>
> > Depends heavily on the design.  Xilinx packs tighter for certain
> > arithmetic because of the structure of the LUT and carry chain: Altera's
> > carry chain through stratix breaks the 4 lut into a pair of 3 LUTs, one
> > for sum one for carry so it limits the number of inputs per bit.
>
> (snip)
>
> I still miss the XC4000 series where the carry chain was separate
> from the LUTs, for convenient implementation of saturating adders
> and MAX(a,b) functions by feeding the carry out or overflow
> back to an LUT input.
>
> -- glen

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

>> Fire your synthesize tool and see how much resources you'd really need!

Yes, this is my point,
Both structures have different resources, when write your code; your code
stile make the difference.

Walter.


"Arash Salarian" <arash.salarian@epfl.ch> a &#4294967295;crit dans le message de
news:417397f6$1@epflnews.epfl.ch...
> "Walter Gallegos" <walter@chasque.apc.org> wrote in message
> news:10n2h60q87tig87@news.supernews.com...
> > The answare is
> >
> >      1 slice into a Spartan 3
> >    16 LE   into a MAX-II
> >
> > Can you compare this architectures as  1 Slice = 2 LE's  ?
> >
>
> I agree that there some areas that you can't simply compare the two
> architectures. For example, I had an old design with an Altera 10K series
> that used a fully async RAM block. Now, move it to a Spartan 3
architecture
> and you see that you should use the whole chip just to make that block of
> async RAM!
> However, it is perfectly understandable that a user might need to compare
> different available options and to do this, he/she would need to have
rough
> estimates to compare a Xilinx device to that of Altera. For example,
> recently I had this interesting offer for a an FPGA prototype  board with
> the same price of $99 for an Altern EP1C12 or a Xilinx XC3S400. I would
like
> to use a prototype board for very different designs so I had to compare
> between the two chips. As I program in VHDL and use synthesize tools, I
> don't really care for any specific architecture (unless something like
your
> example or my example above happens) and the thing that matters in cases
> like that is you only look for the BIGGER FPGA. To do it, you need to
> compare and to compare you can only use rough estimates.
> Personally, I find the simple equation of 1 Slice = 2 LE a very good rough
> estimate and for many designs it gives you a good answer. You have a very
> specific design and need a very good answer? Fire your synthesize tool and
> see how much resources you'd really need!
>
>