Epp interface with Cyclone

I want to realize an EPP interface using Altera FPGA Cyclone (read and write
operation) but I have some synchronization problems. I want to sample datas
from a 4 bits chip,  storing them in a ZBT SRAM memory (Flow trought) and
later acquiring them by parallel port. the chip works at 10MHz but the pll
on board can't divide input clock of 20MHz for 2. How can I divide the
frequency?
thanks.  Does anyone do something like that?

Hi Michelle,

I think Cyclone PLL needs xtal input > 15 MHz, also cannot lock on
frequencies below 15 MHz....
Also think that 10 MHz for a PC EPP port is rather high, try 1 MHz to start
with.
You must synchronise PC EPP signals (strobes, wait ) with the Internal
Cyclone signals, use the standard 2 flip-flop synchronisers for this.
regards

Ron Proveniers
www.info-trade.nl


"Michele Bergo" <michelebergo@libero.it> schreef in bericht
news:%ORid.18871$Ni.665341@twister1.libero.it...
> I want to realize an EPP interface using Altera FPGA Cyclone (read and
write
> operation) but I have some synchronization problems. I want to sample
datas
> from a 4 bits chip,  storing them in a ZBT SRAM memory (Flow trought) and
> later acquiring them by parallel port. the chip works at 10MHz but the pll
> on board can't divide input clock of 20MHz for 2. How can I divide the
> frequency?
> thanks.  Does anyone do something like that?
>
>

Use a simple counter, in this case a single D-Type Flip Flop.You don't need
a PLL if you need sub factors or the main clock.

Victor
http://www.zertec.co.za



"Michele Bergo" <michelebergo@libero.it> wrote in message
news:%ORid.18871$Ni.665341@twister1.libero.it...
> I want to realize an EPP interface using Altera FPGA Cyclone (read and
write
> operation) but I have some synchronization problems. I want to sample
datas
> from a 4 bits chip,  storing them in a ZBT SRAM memory (Flow trought) and
> later acquiring them by parallel port. the chip works at 10MHz but the pll
> on board can't divide input clock of 20MHz for 2. How can I divide the
> frequency?
> thanks.  Does anyone do something like that?
>
>

"ron" <spamrprovo@xs4all.nl> ha scritto nel messaggio
news:418cee87$0$21106$e4fe514c@news.xs4all.nl...
> Hi Michelle,
>
> I think Cyclone PLL needs xtal input > 15 MHz, also cannot lock on
> frequencies below 15 MHz....
> Also think that 10 MHz for a PC EPP port is rather high, try 1 MHz to
start
> with.
> You must synchronise PC EPP signals (strobes, wait ) with the Internal
> Cyclone signals, use the standard 2 flip-flop synchronisers for this.
> regards
>
> Ron Proveniers
> www.info-trade.nl
>
>
> "Michele Bergo" <michelebergo@libero.it> schreef in bericht
> news:%ORid.18871$Ni.665341@twister1.libero.it...
> > I want to realize an EPP interface using Altera FPGA Cyclone (read and
> write
> > operation) but I have some synchronization problems. I want to sample
> datas
> > from a 4 bits chip,  storing them in a ZBT SRAM memory (Flow trought)
and
> > later acquiring them by parallel port. the chip works at 10MHz but the
pll
> > on board can't divide input clock of 20MHz for 2. How can I divide the
> > frequency?
> > thanks.  Does anyone do something like that?
> >
> >
> Thank u very much

"Victor Schutte" <victors@mweb.co.za> ha scritto nel messaggio
news:cml4l6$7i8$1@ctb-nnrp2.saix.net...
> Use a simple counter, in this case a single D-Type Flip Flop.You don't
need
> a PLL if you need sub factors or the main clock.
>
> Victor
> http://www.zertec.co.za
>
>
>
> "Michele Bergo" <michelebergo@libero.it> wrote in message
> news:%ORid.18871$Ni.665341@twister1.libero.it...
> > I want to realize an EPP interface using Altera FPGA Cyclone (read and
> write
> > operation) but I have some synchronization problems. I want to sample
> datas
> > from a 4 bits chip,  storing them in a ZBT SRAM memory (Flow trought)
and
> > later acquiring them by parallel port. the chip works at 10MHz but the
pll
> > on board can't divide input clock of 20MHz for 2. How can I divide the
> > frequency?
> > thanks.  Does anyone do something like that?
> >
> >
thank u very much