Metastability MTBF in Cyclone

Hi All,

I have a Cyclone application with a long lifetime and a high realibility 
requirement (i.e. no subsequent CRC's and retries, the IGBT just turns on)

I am trying to assess the MTBF of metastable events. I have 166MHz clock and 
10kHz async. inputs with a single sync. latch. Latencies are best avoided so 
I'd rather not double sync. unless I have to.

The Altera app. note gives an expression for MTBF based on the metastable 
time Tmet and two device dependant parameters (C1 and C2)

Are these parameter values available for Cyclone ?

Thanks,
Gary

Since I do not work for Altera, I cannot comment on their parameter
values. But I can give you some general inputs:
Your biggest problem is the 166 MHz clock rate, i.e. the short 6 ns
clock period. You must do everything humanly possible to keep the
interconnect + logic from the synchronizing flip-flop's Q to the next
destination"s D as short as possible. If Altera flip-flops are similar
to the Xilinx flip-flops that I have measured (and there is every
reason to assume they are) then the metastable MTBF will change by a
factor of a million (!) for every half nanosecond of extra "breathing
room" you have on that path.
And it would be really desirable to drive only one D from that Q, i.e.
do not fan out the logic at that point.
I think you can succeed.
Peter Alfke, Xilinx Applications.
==============================
Gary Pace wrote:
> Hi All,
>
> I have a Cyclone application with a long lifetime and a high
realibility
> requirement (i.e. no subsequent CRC's and retries, the IGBT just
turns on)
>
> I am trying to assess the MTBF of metastable events. I have 166MHz
clock and
> 10kHz async. inputs with a single sync. latch. Latencies are best
avoided so
> I'd rather not double sync. unless I have to.
>
> The Altera app. note gives an expression for MTBF based on the
metastable
> time Tmet and two device dependant parameters (C1 and C2)
>
> Are these parameter values available for Cyclone ?
> 
> Thanks,
> Gary

Peter - Do you have any documentation on this?
Thanks!
Ben

"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1107227844.242806.124150@c13g2000cwb.googlegroups.com...
> Since I do not work for Altera, I cannot comment on their parameter
> values. But I can give you some general inputs:
> Your biggest problem is the 166 MHz clock rate, i.e. the short 6 ns
> clock period. You must do everything humanly possible to keep the
> interconnect + logic from the synchronizing flip-flop's Q to the next
> destination"s D as short as possible. If Altera flip-flops are similar
> to the Xilinx flip-flops that I have measured (and there is every
> reason to assume they are) then the metastable MTBF will change by a
> factor of a million (!) for every half nanosecond of extra "breathing
> room" you have on that path.
> And it would be really desirable to drive only one D from that Q, i.e.
> do not fan out the logic at that point.
> I think you can succeed.
> Peter Alfke, Xilinx Applications.
> ==============================
> Gary Pace wrote:
> > Hi All,
> >
> > I have a Cyclone application with a long lifetime and a high
> realibility
> > requirement (i.e. no subsequent CRC's and retries, the IGBT just
> turns on)
> >
> > I am trying to assess the MTBF of metastable events. I have 166MHz
> clock and
> > 10kHz async. inputs with a single sync. latch. Latencies are best
> avoided so
> > I'd rather not double sync. unless I have to.
> >
> > The Altera app. note gives an expression for MTBF based on the
> metastable
> > time Tmet and two device dependant parameters (C1 and C2)
> >
> > Are these parameter values available for Cyclone ?
> >
> > Thanks,
> > Gary
>

Well, I can obviously not speak for Altera ;-)
But go to the Xilinx website and either scan the TechXclusives (good
stuff!) or search for "metastable" or for my name, and you will find
quantitative data,
XAPP094 is the best source, but it is being refurbished right now...
Peter Alfke, Xilinx Applications