what's the difference between syn FIFO and asyn FIFO?

Hi,
    I'm designing a itu656 video data format decoder, where I need use a
FIFO to send the active pixel to the next module for processing.
    But, as you known, I'm a newbie in EDA field. I can't say what kind of
FIFO will be useful in this design and I don't know how to use the xilinx
FIFO ip core.
    Anybody has a project like this? Can you give me a application note of
how to use the xilinx FIFO IP Core?
    Thank you!
                                                                        willie
CHEN
                                                                        kmust,china

Willie,

Synchronous FIFOs are used to buffer data between logic in the same
clock domain.  Async FIFOs are required if you are buffering data where
the write side is in a different clock domain as the read side.   As
for the application notes, I believe the Core Generator contains links
to IP documentation.

John