using a SDRAM FIFO

Hi there,

I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using 
Microblaze soft-core.
My intention is to save packets recieved from the network in SDRAM for 
later process.
I have been thinking of using a SDRAM FIFO to be able to process the 
packets after been saved in memory.
As I am working with EDK 6.3 I was thinking of using a FIFO IP core to 
be used in SDRAM.
Can this be done this way? EDK doesn't include any FIFO IP core on the 
predesigned cores.
I also have thought of creating a FIFO with Xilinx COREGEN and then 
including the FIFO in my EDK project but I can'f figure the way of 
exporting the .vhd files created by COREGEN into my EDK project.
Has anyone ever used a FIFO in external memory with positive results? 
Which is the best way to do this?
Any advice will be appreciated since I am quite a newbie with FPGA's.

Thanks in advance.

Adrian Mora.

Yes, a Fifo in SDRAM is commonly done.

Not sure about how you're approaching it? You'll need an "SDRAM
controller" of some sort to interface to the external memory. That can
be quite simple if you're going around the SDRAM pretty quickly, as the
accesses will negate the need for refresh cycles, especially if your
data is video or audio and can tolerate occasional bit errors in the
worst case. Then you'll need some on-chip Fifos to buffer up a block of
data for DMA burst into or out of SDRAM. You'll then need to create
some controlling logic to sequence the DMA bursts, track your write and
read pointers etc. Depending on your level of experience it's anything
from a few hours work to a couple of weeks.

I'm not sure if there's freeware out there that does it all for you?
Could be, but in my experience it can often take as long to get on top
of a piece of freeware as it does to design it from scratch for
oneself.


adrian wrote:
> Hi there,
>
> I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using
> Microblaze soft-core.
> My intention is to save packets recieved from the network in SDRAM
for
> later process.
> I have been thinking of using a SDRAM FIFO to be able to process the
> packets after been saved in memory.
> As I am working with EDK 6.3 I was thinking of using a FIFO IP core
to
> be used in SDRAM.
> Can this be done this way? EDK doesn't include any FIFO IP core on
the
> predesigned cores.
> I also have thought of creating a FIFO with Xilinx COREGEN and then
> including the FIFO in my EDK project but I can'f figure the way of
> exporting the .vhd files created by COREGEN into my EDK project.
> Has anyone ever used a FIFO in external memory with positive results?

> Which is the best way to do this?
> Any advice will be appreciated since I am quite a newbie with FPGA's.
> 
> Thanks in advance.
> 
> Adrian Mora.

Adrian,
Reinventing the wheel? just use the ethernet controller (which has fifos 
by the way, to cross the clock domains for the recovered ethernet clk to 
OPB clock) and store the packets with DMA in SDRAM

Or
use a PC (software only) - if you are not going to process the packets 
on the fly the PC will do.
Aurash

adrian wrote:

> Hi there,
>
> I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using 
> Microblaze soft-core.
> My intention is to save packets recieved from the network in SDRAM for 
> later process.
> I have been thinking of using a SDRAM FIFO to be able to process the 
> packets after been saved in memory.
> As I am working with EDK 6.3 I was thinking of using a FIFO IP core to 
> be used in SDRAM.
> Can this be done this way? EDK doesn't include any FIFO IP core on the 
> predesigned cores.
> I also have thought of creating a FIFO with Xilinx COREGEN and then 
> including the FIFO in my EDK project but I can'f figure the way of 
> exporting the .vhd files created by COREGEN into my EDK project.
> Has anyone ever used a FIFO in external memory with positive results? 
> Which is the best way to do this?
> Any advice will be appreciated since I am quite a newbie with FPGA's.
>
> Thanks in advance.
>
> Adrian Mora.



-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Adrian,

What you are describing sounds very much like XAPP536 which
we also call Gigabit System Reference Design (GSRD)
http://www.xilinx.com/gsrd

There are two difference here, first it uses the PowerPC and
not MicroBlaze, second it uses DDR-SDRAM instead of SDRAM. From
a conceptual point of view though it can provide you with a
good starting point and runs on a variety of platforms.

I'm curious about one thing, since you are targeting a XC2VP7
device why are you planning on using MicroBlaze instead of
the embedded PowerPC for this project?

Ed


adrian wrote:
> Hi there,
> 
> I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using 
> Microblaze soft-core.
> My intention is to save packets recieved from the network in SDRAM for 
> later process.
> I have been thinking of using a SDRAM FIFO to be able to process the 
> packets after been saved in memory.
> As I am working with EDK 6.3 I was thinking of using a FIFO IP core to 
> be used in SDRAM.
> Can this be done this way? EDK doesn't include any FIFO IP core on the 
> predesigned cores.
> I also have thought of creating a FIFO with Xilinx COREGEN and then 
> including the FIFO in my EDK project but I can'f figure the way of 
> exporting the .vhd files created by COREGEN into my EDK project.
> Has anyone ever used a FIFO in external memory with positive results? 
> Which is the best way to do this?
> Any advice will be appreciated since I am quite a newbie with FPGA's.
> 
> Thanks in advance.
> 
> Adrian Mora.