Accessing BRAM as a SRAM

Hallo,
I have a Spartan 3 Starter Board.

I should use a BRAM as a SRAM. I have read that BRAM_if_controller should do
it.

I would know if it is possible to connect a dual port ram to the controller.
In this way I could access BRAM as 1MB RAM on board though C software and I
could also make a sequential reading (hardware, with a counter which
generates addresses) on the same BRAM to send data to board pins
indipendently from which I am writing or reading though software.

If it is possbile, there is someone who know how?

Many Thanks
Marco Toschi

"Peter Alfke" <peter@xilinx.com> wrote in message
news:1117229140.816601.128360@g44g2000cwa.googlegroups.com...
> Marco, I see that nobody sent you an answer. That may be because it is
> difficult to understand what you really need.
> I doubt that you have megabytes of RAM on a small Spartan eval board.
> The BlockRAM is a static RAM. It has two totally independent ports,
> each with their own addressing, control, and timing. And you can even
> have different widt/depth ratios on the two ports.
> Note that you need a clock to access the BlockRAM. Just changing the
> address does nothing, you need a clock, even for a read operation.
> Think about it, and tell us (or me) what your real problem is.
> Peter Alfke, Xilinx Applications
>

(On the starter board there is 1 MByte of RAM)

I would access the BlockRam through software as I can access the 1MB RAM of
starter board: I would create variables, etc... into BlockRam.

I have read about the opb bram controller, but I don't have found
information about the way to use it through software.

I hope it is more clear...

Thanks
Marco

Marco, I see that nobody sent you an answer. That may be because it is
difficult to understand what you really need.
I doubt that you have megabytes of RAM on a small Spartan eval board.
The BlockRAM is a static RAM. It has two totally independent ports,
each with their own addressing, control, and timing. And you can even
have different widt/depth ratios on the two ports.
Note that you need a clock to access the BlockRAM. Just changing the
address does nothing, you need a clock, even for a read operation.
Think about it, and tell us (or me) what your real problem is.
Peter Alfke, Xilinx Applications

On Fri, 27 May 2005 16:42:31 +0200, "Marco" <marcotoschi_no_spam@email.it> wrote:
>Hallo,

Hello,

>I have a Spartan 3 Starter Board.
>
>I should use a BRAM as a SRAM. I have read that BRAM_if_controller should do
>it.

This might make sense if you are implementing a soft processor in
the FPGA. If you are instead building logic without a processor in
the FPGA, then this is unneeded. Just connect the BRAM up to your logic.

>I would know if it is possible to connect a dual port ram to the controller.

Depends on why you think you need a controller. It usually only makes
sense to use controllers like this if there is a CPU in the FPGA.

>In this way I could access BRAM as 1MB RAM on board though C software and I

This does not make sense. The amount of BRAM in the FPGA is not 1MB.
The XC3S200 FPGA has 12 blocks of 2K bytes (9 bit bytes) for a total
of 221184 bits. There is 1MB of SRAM on the board outside the FPGA,
but this is not called BRAM. Reading and writing this SRAM is "just a matter
of hardware design".

Where do you think this C code is running? inside the fpga, or on your
host computer? How are you planning to talk to your board from your
host computer?

>could also make a sequential reading (hardware, with a counter which
>generates addresses) on the same BRAM to send data to board pins
>indipendently from which I am writing or reading though software.

Again, the issue is where you think this software is running. FPGAs
do not run C code, unless you have designed (or got it from somewhere else)
a CPU and loaded it into the FPGA. You may want to learn about Microblaze
and Picoblaze on the Xilinx website.

>If it is possbile, there is someone who know how?

I don't think you understand the environment well enough yet. When you
can answer alll my above questions, then you can get more help.

Philip



>Many Thanks
>Marco Toschi
>

===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG

"Philip Freidin" <philip@fliptronics.com> wrote in message
news:045g91ls6djblmpdt86mjcmg2tfvvu2k4a@4ax.com...
> On Fri, 27 May 2005 16:42:31 +0200, "Marco" <marcotoschi_no_spam@email.it>
wrote:
> >Hallo,
>
> Hello,
>
> >I have a Spartan 3 Starter Board.
> >
> >I should use a BRAM as a SRAM. I have read that BRAM_if_controller should
do
> >it.
>
> This might make sense if you are implementing a soft processor in
> the FPGA. If you are instead building logic without a processor in
> the FPGA, then this is unneeded. Just connect the BRAM up to your logic.


I'm developing a microcontroller based on microblaze.


>
> >I would know if it is possible to connect a dual port ram to the
controller.
>
> Depends on why you think you need a controller. It usually only makes
> sense to use controllers like this if there is a CPU in the FPGA.
>
> >In this way I could access BRAM as 1MB RAM on board though C software and
I
>
> This does not make sense. The amount of BRAM in the FPGA is not 1MB.
> The XC3S200 FPGA has 12 blocks of 2K bytes (9 bit bytes) for a total
> of 221184 bits. There is 1MB of SRAM on the board outside the FPGA,
> but this is not called BRAM. Reading and writing this SRAM is "just a
matter
> of hardware design".


I know that BRAM is not 1MByte. I understand also to have written something
not understandable, sorry!

I need only 32KByes of BRAM to make a video memory for a black/white lcd
display.



>
> Where do you think this C code is running? inside the fpga, or on your
> host computer? How are you planning to talk to your board from your
> host computer?



Inside FPGA, loaded from flash with boot support and copied into 1MByte RAM




>
> >could also make a sequential reading (hardware, with a counter which
> >generates addresses) on the same BRAM to send data to board pins
> >indipendently from which I am writing or reading though software.
>
> Again, the issue is where you think this software is running. FPGAs
> do not run C code, unless you have designed (or got it from somewhere
else)
> a CPU and loaded it into the FPGA. You may want to learn about Microblaze
> and Picoblaze on the Xilinx website.


I must develop a lcd display controller. The other parts are ready for
running (some taken by edk ip cores, some mades by me)



I hope now my trouble is more clear.


Thanks
Marco

I need only 20 Kbit into BRAM... I made a mistake into previous message.

On Sat, 28 May 2005 09:47:28 +0200, "Marco" <marcotoschi_no_spam@email.it> wrote:
>"Philip Freidin" <philip@fliptronics.com> wrote in message
>news:045g91ls6djblmpdt86mjcmg2tfvvu2k4a@4ax.com...
>> On Fri, 27 May 2005 16:42:31 +0200, "Marco" <marcotoschi_no_spam@email.it>
>wrote:
>> >Hallo,
>>
>> Hello,
>>
>> >I have a Spartan 3 Starter Board.
>> >
>> >I should use a BRAM as a SRAM. I have read that BRAM_if_controller should
>do
>> >it.
>>
>> This might make sense if you are implementing a soft processor in
>> the FPGA. If you are instead building logic without a processor in
>> the FPGA, then this is unneeded. Just connect the BRAM up to your logic.
>
>I'm developing a microcontroller based on microblaze.

Ok, now it makes more sense. As you have written, you should probably
be using "OPB BRAM Controller", which is described in the Xilinx document
DS468 at:

    http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=OPB_BRAM_Controller&iLanguageID=1

>>
>> >I would know if it is possible to connect a dual port ram to the
>controller.

Yes you can do this. The BRAM is described in the Libraries guide at:

   http://toolbox.xilinx.com/docsan/xilinx7/books/manuals.htm

and the specific item you need to look for is RAMB16_Sm_Sn

>> Depends on why you think you need a controller. It usually only makes
>> sense to use controllers like this if there is a CPU in the FPGA.
>>
>> >In this way I could access BRAM as 1MB RAM on board though C software and
>I
>>
>> This does not make sense. The amount of BRAM in the FPGA is not 1MB.
>> The XC3S200 FPGA has 12 blocks of 2K bytes (9 bit bytes) for a total
>> of 221184 bits. There is 1MB of SRAM on the board outside the FPGA,
>> but this is not called BRAM. Reading and writing this SRAM is "just a
>> matter of hardware design".
>
>
>I know that BRAM is not 1MByte. I understand also to have written something
>not understandable, sorry!
>
>I need only 32KByes of BRAM to make a video memory for a black/white lcd
>display.

Later:  I need only 20 Kbit into BRAM... I made a mistake into previous message.

A BRAM is either 16K bits (for widths 1, 2, 4 bits) or 18K bits (width 9, 18, 36).

From a performance point of view, you get to move more data per cycle with
wider transfers. But the BRAM interface to microblaze only supports up to
32 bits. This would suggest (but it is not mandatory) that you would set
up the BRAM in a by 36 bit width, and just not use 4 bits of the data path
from the BRAM. This would give you 16K bits (RAMB16_S36_S36). 

Since you need a total of 20K bits, then you need to have 2 BRAMs. If you
set them both for 18 bits wide (1K deep), and addressed them at the same time,
you would have 36 bits wide by 1K, of which you would use 32 bits by 1K,
for a total useable size of 32K bits. All of the above would apply to just
1 of the two ports of each BRAM. The other port is addressed by what ever
hardware you design to read the data out and send it to your LCD.
The BRAM instantiation would be 2 x RAMB16_S18_S18 



Note: 1) The BRAM will have to be instantiated.
      2) The second port can be a different width than the first port,
         but the complexities of how that affects addressing may be
         something you dont want to deal with initially.

>> Where do you think this C code is running? inside the fpga, or on your
>> host computer? How are you planning to talk to your board from your
>> host computer?
>
>Inside FPGA, loaded from flash with boot support and copied into 1MByte RAM

Ok. The interface from the external SRAM to microblaze for code fetch
is separate from all the stuff that I have written above. You should
get this working first (as a confidence booster) befor you start on adding
the BRAM and LCD interface.

>>
>> >could also make a sequential reading (hardware, with a counter which
>> >generates addresses) on the same BRAM to send data to board pins
>> >indipendently from which I am writing or reading though software.
>>
>> Again, the issue is where you think this software is running. FPGAs
>> do not run C code, unless you have designed (or got it from somewhere
>else)
>> a CPU and loaded it into the FPGA. You may want to learn about Microblaze
>> and Picoblaze on the Xilinx website.
>
>
>I must develop a lcd display controller.

Right.

>The other parts are ready for >running (some taken by edk ip cores, some mades by me)

Good.

>I hope now my trouble is more clear.

I think so. I hope my notes are of help to you.

>Thanks
>Marco


Good luck,
Philip



===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG

After reading every message I thought:

1) Use OPB_BRAM_IF_CONTROLLER
2) Generate a Dual Port Ram with Coregenerator of 19200 addresses with 4bit,
and 9600 addresses with 8 bit.
3) Connect the 9600 addresses with 8bit ram to the controller.
4) Write the logic blocks to syncronize lcd display with 19200 addr. with 4
bit ram (already made).

Now I have the following questions:

1) In what way could I connect controller with dual port ram??? EDK does it
automatically, but I'm not able to view or edit ram hdl file and I can't
customize it with logic block for syncronization.

2) When point 1 is done which C function should I use to perform read or
write into ram?    Xio_in8 and Xio_out8 ????


Many Thanks to everyone, specially for your patience!
Marco