HDL simple survey - what do you actually use

VHDL + VUnit (https://vunit.github.io/index.html)

Regards,
Lars

VHDL + VUnit (https://vunit.github.io/index.html)

Regards,
Lars

VHDL for design.
VHDL + UVVM (Universal VHDL Verification Methodology, Open source) for verification 
https://github.com/UVVM/UVVM_All

Using VHDL with a good testbench architecture and a good infrastructure library allows very efficient verification.
BTW: UVVM also comes with open source BFMs (Bus Functional Models) and VVCs (VHDL Verification Components) for interfaces like AIX4-lite, AXI4-stream, Avalon MM, UART, I2C, SPI.

> 
> VHDL for RTL (primarily FPGAs but ASIC in the past).   VHDL + OSVVM for testbenches.
> 

Same here. Even when not using OSVVM, I use VHDL primarly for my 
testbenches, sometimes with PSL when needed.