VHDL + VUnit (https://vunit.github.io/index.html) Regards, Lars
HDL simple survey - what do you actually use
Started by ●January 10, 2018
Reply by ●February 26, 20182018-02-26
Reply by ●February 26, 20182018-02-26
Reply by ●February 27, 20182018-02-27
VHDL for design. VHDL + UVVM (Universal VHDL Verification Methodology, Open source) for verification https://github.com/UVVM/UVVM_All Using VHDL with a good testbench architecture and a good infrastructure library allows very efficient verification. BTW: UVVM also comes with open source BFMs (Bus Functional Models) and VVCs (VHDL Verification Components) for interfaces like AIX4-lite, AXI4-stream, Avalon MM, UART, I2C, SPI.
Reply by ●March 9, 20182018-03-09