Sharing VHDL Verification IP

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community has previously been difficult because there was no standardised way of interfacing to and controlling these VVCs. A solution on this challenge could easily reduce the project verification time by 20 to 80%, and at the same time improve the FPGA quality.

The open source UVVM has over the last two years standardised the command interface, integration, debugging and internal architecture of VHDL Verification Components and clearly shown that a standardisation was in deed both possible and extremely efficient. Open source VVCs have been released for AXI4-lite, AXI4-stream, Avalon MM, I2C, SPI, SBI, UART and GPIO, - showing how easy it is to implement testbenches and write test cases using this standardised methodology.

Due to this standardisation, FPGA designers world-wide have recently started asking for more cooperation on UVVM compliant VVCs inside the VHDL community. As this is actually the main intention behind standardising VVCs, we have now decided to facilitate a Verification IP cooperation. For this purpose we have opened a new repository on Github for sharing VHDL VIP next to the UVVM repository.
https://github.com/UVVM/UVVM_3rd_party_VIP

This new repository is intended to link to any UVVM compatible Verification IP; - VVC, BFM or other. We have chosen not to include any VIP directly inside this repository, as all 3rd party VIP will be the property of and maintained by the 3rd party company or designer.

Any 3rd part VIP will automatically be UVVM compliant given that the designers have used the provided templates or scripts from UVVM. This has of course the major benefit that all UVVM compliant VIP can be controlled and accessed exactly the same way and that they will work together. There is however no way we can guarantee the functionality of the DUT interface/protocol handled by 3rd party VVC or BFM designers, so this will be the full responsibility of the VIP provider. Any question regarding the VVC should therefore be addressed to this provider. Bitvis will not qualify any 3rd party VIP, but we assume the community will very soon give useful feedback.

Open source Verification IP is great, and UVVM with its provided BFMs and VVCs are all open source and free, - but we also welcome commercial VIP and will link to this in the same way as open source. It is important for VHDL designers to get the full overview of what is available, and it is up to them to decide whether a commercial VIP is ok. All commercial aspects must be handled directly between the buyer and the seller. Bitvis has no role in this.

Note that even if UVVM has standardised the VHDL testbench architecture for efficient verification, you may still pick only the parts you like. Thus you can pick only a single BFM or VVC from UVVM if you like, and use this in your testbench together with your own and 3rd party verification IP.

We now really hope that the VHDL community will use this opportunity to make us all more efficient. Have a look at this on Github and start the process :-)

(This article was also published on LinkedIn. Articles there may also include figures, which sometimes is very useful...  
https://www.linkedin.com/pulse/sharing-vhdl-verification-ip-espen-tallaksen/)