Testbench using Modelsim/VHDL - simple signal generation problem

It would be a case if delta cycle in simulator is set to the same
value as clk period.

If you see it go high late.. then it would tend to disagree with the results
you printed on the first page.

In saying that.. if you are looking in the wrong place this is quite
possible
if you are peeking in a process.. then check the sensitivity list.. that's
the usual culprit when things don't happen when you expect.

Simon


<fastgreen2000@yahoo.com> wrote in message
news:1128090988.252193.220510@o13g2000cwo.googlegroups.com...
> Yes, I'm doing just that for creating clock,  and your post shed some
> light on what I wasn't paying attention to, but...
>
> I'm still confused.  In the following testbench code, shouldn't it wait
> for a certain rising edge (whatever time it might correspond to), and
> assert 'sig1', at the time reported by 'now'?  What I see is 'sig1' get
> asserted one clock after that.
>
> line 1 : wait until rising_edge(clk);
> line 2 : write (L, string'("1st rising edge : " & image(now)));
> line 3 : writeline (output, L);
> line 4 : sig1  <= '1';       -- I see this signal go high at 'now' + 1
> more clock cycle??
>                                        -- note that lines 2,3,4 are
> occuring after the rising edge.
>