Need Advice regarding Interfacing of Max9850 audio DAC with spartan 6 FPGA

Started by Swapnil Patil September 7, 2018
Hello Folks,

I am trying to interface MAX9850 Audio DAC with spartan 6 FPGA with I2C
Interfacing.
I'm Using VHDL Language For coding.
 Does Someone worked on this before? or worked related to this.

 Things need to know I am using only these two for interfacing.So For clocking what
should i do?(can i use fpga clock for driving master clock)

what audio data format to choose?Right justified or left or I2s

I just need to hear audio from Max9850 audio jack.
 what other factor i need to take into account....
On 07/09/2018 11:11, Swapnil Patil wrote:
> Hello Folks, > > I am trying to interface MAX9850 Audio DAC with spartan 6 FPGA with I2C
Interfacing.
> I'm Using VHDL Language For coding. > Does Someone worked on this before? or worked related to this. > > Things need to know I am using only these two for interfacing.So For clocking
what should i do?(can i use fpga clock for driving master clock)
> > what audio data format to choose?Right justified or left or I2s > > I just need to hear audio from Max9850 audio jack. > what other factor i need to take into account.... >
I think that you need to read the data sheets for the chips very carefully - it is not possible to drive the data to an audio DAC via I2C. Like many others the MAX9850 has an I2C interface for configuration but uses the classic MCLK, BCLK,LRCLK and SD (Serial Data) for the audio data. If you drive from an FPGA the choice between left justified, right justified or I2S is unimportant - all can easily be achieved. It isn't that hard to implement both the I2C and audio data interfaces on an FPGA. You can use an FPGA derived clock for the master clock (assuming you are not looking for ultimate audio quality so don't care about jitter). The Maxim data sheet will tell you about relationships between master clock and data clocks and audio data. MK