74 logic to CPLD. how easy for a Newbie?

Thank you everyone for your advice,

I think I have been inspired sufficiently to get a dev kit to play
with. This is a very mature product that still works really well;
judging from your responses however, I feel it would be an important
step for me to be able to ditch thinking in 74 numbers and it's
something I really should have done before (Plus a big wad a brownie
points never hurts).

One more quick question though..

My design also has the following elements, which of these couldn't get
squeezed into a CPLD?

4046 PLL's (Phase comparator 2)
various Comparators


Thanks again everyone.

Carl.

On 22 Oct 2003 01:02:24 -0700, jiz_king@hotmail.com (Carl) wrote:

>Thank you everyone for your advice,
>
>I think I have been inspired sufficiently to get a dev kit to play
>with. This is a very mature product that still works really well;
>judging from your responses however, I feel it would be an important
>step for me to be able to ditch thinking in 74 numbers and it's
>something I really should have done before (Plus a big wad a brownie
>points never hurts).
>
>One more quick question though..
>
>My design also has the following elements, which of these couldn't get
>squeezed into a CPLD?


>4046 PLL's (Phase comparator 2)

In theory, you can do this in a CPLD.  In practice, the performance
may be poor with respect to the original.

Note that the 4046 PC2 isn't a particularly good phase comparator to
start with (with respect to better designs such as the 74HC9046).
The '9046 has a current source & sink output that cannot be done
(directly) in a CPLD.
The '4046 has a tristate output that's just like a regular tristate
output on a CPLD.

>various Comparators

Maybe, maybe not.  
Some CPLDs have schmitt trigger inputs.
Some FPGAs have differential inputs (e.g. LVDS) that behave like a
comparator.
Don't expect any CPLD or FPGA to give you low noise, precision
thresholds like a comparator though.

Regards,
Allan.

"Kasper Pedersen" <ngfilter@kasperkp.dk> wrote in message
news:3f9570cb$0$45335$edfadb0f@dread11.news.tele.dk...
>
> "Carl" <jiz_king@hotmail.com> wrote in message
> news:8aec9d92.0310210623.443ba2d5@posting.google.com...
> > I have never used PLD's before, but have used PIC's (asm) and was
> > wondering if it is realistic for me to grasp enough of PLD design (not
> > necessarily VHDL) to implement some simple logic functions within a
> > month or so?
> >
> > Or is this likely to take far longer?
>
> Assuming you're not learning logic from scratch:
> When I first started with CPLD's I was using a rather early Xilinx
> Foundation,
> covertly provided to me, and it went something like this:
> Day 0: Be friendly towards the FAE when he's on-site anyway. Get a hint.
> Day 1: Get the tool installed. Why the hell won't my schematic of a
> simple buffer translate?
> Day 2: Discovered that I needed I/O buffers. Place a single counter into
> the design, figure out how to put the pins where I want them. It
> translates and fits! Build a small board with an oscillator, an XC9536,
> and a LED. Borrow a Parallel-III cable.
> Day 3: Programming works, LED is blinking (very quickly). Conclude that
> this is feasible.
> Day 6: Call the friendly FAE. "This is a tool bug. Do this instead." Get
> a few tricks and nasty jokes.
> Day 10: Create a better Parallel-III cable, give back the original.

I bought a Parallel-III cable years ago, never used it though, but am
"close" to using it now. What were your problems with the cable?

Cheers

Klaus

"Klaus Vestergaard Kragelund" <klauskvik@hotmail.com> wrote in message
news:3f96dcdd$0$9796$edfadb0f@dread14.news.tele.dk...

> I bought a Parallel-III cable years ago, never used it though, but am
> "close" to using it now. What were your problems with the cable?
>

The primary problem is not so much the cable, it's an odd (now
rare/extinct) breed of parallel port:

On some parallel ports, when the driver writes to the port, instead of
just changing, the signal lines will be undefined for around 100 ns.
This results in extra clock pulses and wrong data being clocked into the
device.
The cause is the behaviour of the x86 ISA bus (on which the parallel
port still resides, even in my K7 machine): The write strobe is asserted
before data i stable; For this reason the original IBM design calls for
an edge triggered latch but some used level gated ones.
Certain Compaq, Olivetti, and Siemens Pentium-1 machines had the
problem.


/Kasper

>My design also has the following elements, which of these couldn't get
>squeezed into a CPLD?
>
>4046 PLL's (Phase comparator 2)
>various Comparators

I suggest that you put that on the back burner to start with.

You will have to read the data sheets for the CPLDs you are
interested in, probably many times.  While you are doing that,
keep an eye out for things that match the data sheets of the
parts you are trying to replace.

Basically, CPLDs/PALs work great for traditional digital problems.
That is:
  clumps of FFs (state machines, counters) have a max frequency
  FFs have setup/hold and clock to out
  gates/logic have prop times
All that gets complicated by routing/placement.  For the simple
devices you can generally do it in your head.

If you want to do analog-ish things, you have to find a circuit
that will work given the specs you can find in the data sheet.
(Sometimes you have to use your imagination and/or read between
the lines.)  If you can find the specs you need, then you can
build your circuit.  But I doubt if you will find much that helps
for PLLs or comparators.

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