Xilinx LUT behavior question

Eric,

Yes, he will have problems.

Glitches on LUTs will be the least of his problems.

Austin

Eric Smith wrote:

> I asked about the possibility of glitches on LUT outputs.  Peter gave
> a definitive response, and Symon wrote:
> 
>>You got a good answer from Peter. However, my smarty pants response is to 
>>never put yourself in a position where you care what the answer is! You'd 
>>never clock a FF from the output of a LUT. Would you? ;-)
> 
> 
> I fully agree; my designs are fully synchronous.
> 
> The reason the whole question came up is that a friend is trying to
> cram old TTL logic designs into an FPGA without redesigning them to
> be synchronous, so he has latches, S-R flops, and other horrible stuff.
> I was wondering whether an S-R flop implemented as two cross-coupled
> gates using a LUT for each gate could even be guaranteed to function
> correctly; if LUTs can have output glitches they would not.
> 
> I'm still trying to convince my friend that his approach is likely to
> cause him much grief.
> 
> Eric