Forgot to add that your statement "Because at every node in a state machine a decision must be made to determine where to go and what signals's values should be" is not at all what is going on... unless you want to say that it applies to ALL synthesis operations that transform a human readable logic description into an implementation. I wouldn't call that a 'decision tree', but you may feel differently. Kevin
What is the name of the circuit structure that generates a state machine's jumping signals?
Started by ●December 13, 2018
Reply by ●December 13, 20182018-12-13
Reply by ●December 13, 20182018-12-13
On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote:> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > Hi, > > > > > > What is the name of the circuit structure that generates a state machine's jumping signals? > > > > > > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > > > > > What is the correct name? > > > > > > Thank you. > > > > > > Weng > > > > > > > > > > > Transition or next state logic? > > > > Hans > > www.ht-lab.com > > Hi, > > Sorry, maybe I did not specify my question clearly. > > Here is a code example I would ask for answer: > > type State_Type is ( > S0, S1, ...); > > signal WState, WState_NS : State_Type; > ...; > > a : process(CLK) > begin > if rising_edge(CLK) then > if SINI = '1' then > WState <= S0; > > else > WState <= WState_NS; > end if; > end if; > end process; > > b : process(all) > begin > case WState is > when S0 => > if C1 then > WState_NS <= S1; > > elsif C2 then > WState_NS <= S2; > > else > WState_NS <= S0; > end if; > ...; > end case; > end process; > > Now a synthesizer must generate a signal S0_C1 as follows > > S0_C1 <= not SINI and WState = S0 and C1; > > When S0_C1 is asserted, WState will go from S0 to S1. > > I call signal S0_C1 a jumping signal for the state machine. > > I want to know: > 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > > 2. If there is a systematic circuit structure, what its name is? > > 3. Do you know how Xilinx or Altera generates a circuit for a state machine?First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? Does this make sense? Rick C. Tesla referral code + https://ts.la/richard11209
Reply by ●December 13, 20182018-12-13
On Thursday, December 13, 2018 at 5:19:51 PM UTC-5, gtwrek wrote:> In article <ab41052b-483a-45ff-9000-ca442466d54b@googlegroups.com>, > Weng Tianxiang <wtxwtx@gmail.com> wrote: > > > >It is not about "Mealy" and "Moore" that is about how to design a state machine. > > > >My question is how to generate a state machine in a systematic circuit, including all signals, state outputs and non-state outputs, whether or not how > >complex a state machine structure is. > > > >If there is no systematic circuit structure to fully generate any type of state machines, I would like to invent such circuits and apply for a patent. > > Still not clear on what you're thinking about with regard to a > "systematic" circuit structure. > > A tool to generate a "circuit, including all signals, state outputs and > non-state outputs" pretty much describes a Synthesis tool. And I'd > rhink most of the patents on those things have been filed and granted for a > LONG time. > > I've never really understood the exceptional focus on "state machines" - > it's just logic and registers like any other part of the design. Some > clever folks decided that under very special circumstances, one could > better optimized certain datapaths - and the first "state machine" > optimizer was created. But it's just that an optimization tool - one > that can be used in a limitted set of circumstances. In today's > large designs where random logic is pretty much free, these minor > optimizations don't usually interest me. > > Good luck, > > MarkI think Weng is looking for something very abstract and algorithmic. I believe he is expecting state machine design to be more complex than it is. This is well furrowed ground. Weng, you would do better to look elsewhere. Rick C. Tesla referral code -- https://ts.la/richard11209 PS I am posting my referral link because if anyone wants to buy a Tesla and they use my link you will get free supercharging for six months (as of now for sure) and I will get a brownie point toward a wall connector that I'd like.
Reply by ●December 13, 20182018-12-13
On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote:> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > Hi, > > > > > > > > What is the name of the circuit structure that generates a state machine's jumping signals? > > > > > > > > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > > > > > > > What is the correct name? > > > > > > > > Thank you. > > > > > > > > Weng > > > > > > > > > > > > > > > Transition or next state logic? > > > > > > Hans > > > www.ht-lab.com > > > > Hi, > > > > Sorry, maybe I did not specify my question clearly. > > > > Here is a code example I would ask for answer: > > > > type State_Type is ( > > S0, S1, ...); > > > > signal WState, WState_NS : State_Type; > > ...; > > > > a : process(CLK) > > begin > > if rising_edge(CLK) then > > if SINI = '1' then > > WState <= S0; > > > > else > > WState <= WState_NS; > > end if; > > end if; > > end process; > > > > b : process(all) > > begin > > case WState is > > when S0 => > > if C1 then > > WState_NS <= S1; > > > > elsif C2 then > > WState_NS <= S2; > > > > else > > WState_NS <= S0; > > end if; > > ...; > > end case; > > end process; > > > > Now a synthesizer must generate a signal S0_C1 as follows > > > > S0_C1 <= not SINI and WState = S0 and C1; > > > > When S0_C1 is asserted, WState will go from S0 to S1. > > > > I call signal S0_C1 a jumping signal for the state machine. > > > > I want to know: > > 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > > > > 2. If there is a systematic circuit structure, what its name is? > > > > 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. > > I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. > > There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? > > Does this make sense? > > Rick C. > > Tesla referral code + https://ts.la/richard11209Opps, I should have said if "the state variable WState_NS is two bits" Rick C.
Reply by ●December 13, 20182018-12-13
On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote:> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: > > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > > Hi, > > > > > > > > > > What is the name of the circuit structure that generates a state machine's jumping signals? > > > > > > > > > > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > > > > > > > > > What is the correct name? > > > > > > > > > > Thank you. > > > > > > > > > > Weng > > > > > > > > > > > > > > > > > > > Transition or next state logic? > > > > > > > > Hans > > > > www.ht-lab.com > > > > > > Hi, > > > > > > Sorry, maybe I did not specify my question clearly. > > > > > > Here is a code example I would ask for answer: > > > > > > type State_Type is ( > > > S0, S1, ...); > > > > > > signal WState, WState_NS : State_Type; > > > ...; > > > > > > a : process(CLK) > > > begin > > > if rising_edge(CLK) then > > > if SINI = '1' then > > > WState <= S0; > > > > > > else > > > WState <= WState_NS; > > > end if; > > > end if; > > > end process; > > > > > > b : process(all) > > > begin > > > case WState is > > > when S0 => > > > if C1 then > > > WState_NS <= S1; > > > > > > elsif C2 then > > > WState_NS <= S2; > > > > > > else > > > WState_NS <= S0; > > > end if; > > > ...; > > > end case; > > > end process; > > > > > > Now a synthesizer must generate a signal S0_C1 as follows > > > > > > S0_C1 <= not SINI and WState = S0 and C1; > > > > > > When S0_C1 is asserted, WState will go from S0 to S1. > > > > > > I call signal S0_C1 a jumping signal for the state machine. > > > > > > I want to know: > > > 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > > > > > > 2. If there is a systematic circuit structure, what its name is? > > > > > > 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > > > First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. > > > > I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. > > > > There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? > > > > Does this make sense? > > > > Rick C. > > > > Tesla referral code + https://ts.la/richard11209 > > Opps, I should have said if "the state variable WState_NS is two bits" > > Rick C.Rick, How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. S0_C1 logic is A BIT SIGNAL. Weng
Reply by ●December 14, 20182018-12-14
On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote:> > Rick, > How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. > > S0_C1 logic is A BIT SIGNAL. > > WengThat signal only 'exists' for a one-hot encoded state machine, but not for any other encoding. Given that logic in an FPGA is implemented inside lookup tables even that signal won't actually exist either when implemented in such a fashion. Given that you state without basis "the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1" and I've shown how that is not the case, then I guess it's not so important after all. You can (and will) choose to dismiss what I've said because you're not interested in actual logic synthesis but you were the one who stated the importance of the existence of this signal, yet I've shown your statement to be false. Now, it is possible for you to choose to write your source code in a way that you do have such a discrete signal. But doing so is your personal style choice and has no bearing on any more general concepts such as 'state machine' or any bearing on how anyone else would write their own source code for a 'state machine'. As I previously mentioned, the term 'state machine' is really only a classification term to allow for human discussion, the term has no real importance in logic synthesis or design. Kevin
Reply by ●December 14, 20182018-12-14
On Friday, December 14, 2018 at 4:43:57 AM UTC-8, KJ wrote:> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: > > > > Rick, > > How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. > > > > S0_C1 logic is A BIT SIGNAL. > > > > Weng > > That signal only 'exists' for a one-hot encoded state machine, but not for any other encoding. Given that logic in an FPGA is implemented inside lookup tables even that signal won't actually exist either when implemented in such a fashion. Given that you state without basis "the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1" and I've shown how that is not the case, then I guess it's not so important after all. You can (and will) choose to dismiss what I've said because you're not interested in actual logic synthesis but you were the one who stated the importance of the existence of this signal, yet I've shown your statement to be false. > > Now, it is possible for you to choose to write your source code in a way that you do have such a discrete signal. But doing so is your personal style choice and has no bearing on any more general concepts such as 'state machine' or any bearing on how anyone else would write their own source code for a 'state machine'. As I previously mentioned, the term 'state machine' is really only a classification term to allow for human discussion, the term has no real importance in logic synthesis or design. > > KevinI don't want to start an argument about what I am doing, right or wrong. In a month or so I will publish something that will shows your following 2 claims are wrong: 1. "That signal only 'exists' for a one-hot encoded state machine, but not for any other encoding. " 2. "As I previously mentioned, the term 'state machine' is really only a classification term to allow for human discussion, the term has no real importance in logic synthesis or design." I will give no reason why it is. Weng
Reply by ●December 14, 20182018-12-14
On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote:> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote: > > On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: > > > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > > > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > > > Hi, > > > > > > > > > > > > What is the name of the circuit structure that generates a state machine's jumping signals? > > > > > > > > > > > > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > > > > > > > > > > > What is the correct name? > > > > > > > > > > > > Thank you. > > > > > > > > > > > > Weng > > > > > > > > > > > > > > > > > > > > > > > Transition or next state logic? > > > > > > > > > > Hans > > > > > www.ht-lab.com > > > > > > > > Hi, > > > > > > > > Sorry, maybe I did not specify my question clearly. > > > > > > > > Here is a code example I would ask for answer: > > > > > > > > type State_Type is ( > > > > S0, S1, ...); > > > > > > > > signal WState, WState_NS : State_Type; > > > > ...; > > > > > > > > a : process(CLK) > > > > begin > > > > if rising_edge(CLK) then > > > > if SINI = '1' then > > > > WState <= S0; > > > > > > > > else > > > > WState <= WState_NS; > > > > end if; > > > > end if; > > > > end process; > > > > > > > > b : process(all) > > > > begin > > > > case WState is > > > > when S0 => > > > > if C1 then > > > > WState_NS <= S1; > > > > > > > > elsif C2 then > > > > WState_NS <= S2; > > > > > > > > else > > > > WState_NS <= S0; > > > > end if; > > > > ...; > > > > end case; > > > > end process; > > > > > > > > Now a synthesizer must generate a signal S0_C1 as follows > > > > > > > > S0_C1 <= not SINI and WState = S0 and C1; > > > > > > > > When S0_C1 is asserted, WState will go from S0 to S1. > > > > > > > > I call signal S0_C1 a jumping signal for the state machine. > > > > > > > > I want to know: > > > > 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > > > > > > > > 2. If there is a systematic circuit structure, what its name is? > > > > > > > > 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > > > > > First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. > > > > > > I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. > > > > > > There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? > > > > > > Does this make sense? > > > > > > Rick C. > > > > > > Tesla referral code + https://ts.la/richard11209 > > > > Opps, I should have said if "the state variable WState_NS is two bits" > > > > Rick C. > > Rick, > How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. > > S0_C1 logic is A BIT SIGNAL.That is where you fail to understand. Your code does not include the signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any design tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. So if you only wish to suppose that the signal S0_C1 exists in your theoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. Of your questions:> I want to know: > 1. Is there a systematic circuit structure or a systematic method that can > generate signal S0_C1 and others. I think it is an oldest circuit.Yes, it is called a state/next-state table and is very simple.> 2. If there is a systematic circuit structure, what its name is?We just call it "logic".> 3. Do you know how Xilinx or Altera generates a circuit for a state machine?Yes, they take the logic you define in your HDL and apply the many types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design. Rick C. Tesla referral code -- https://ts.la/richard11209
Reply by ●December 15, 20182018-12-15
On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com wrote:> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: > > On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote: > > > On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: > > > > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > > > > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > > > > Hi, > > > > > > > > > > > > > > What is the name of the circuit structure that generates a state machine's jumping signals? > > > > > > > > > > > > > > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > > > > > > > > > > > > > What is the correct name? > > > > > > > > > > > > > > Thank you. > > > > > > > > > > > > > > Weng > > > > > > > > > > > > > > > > > > > > > > > > > > > Transition or next state logic? > > > > > > > > > > > > Hans > > > > > > www.ht-lab.com > > > > > > > > > > Hi, > > > > > > > > > > Sorry, maybe I did not specify my question clearly. > > > > > > > > > > Here is a code example I would ask for answer: > > > > > > > > > > type State_Type is ( > > > > > S0, S1, ...); > > > > > > > > > > signal WState, WState_NS : State_Type; > > > > > ...; > > > > > > > > > > a : process(CLK) > > > > > begin > > > > > if rising_edge(CLK) then > > > > > if SINI = '1' then > > > > > WState <= S0; > > > > > > > > > > else > > > > > WState <= WState_NS; > > > > > end if; > > > > > end if; > > > > > end process; > > > > > > > > > > b : process(all) > > > > > begin > > > > > case WState is > > > > > when S0 => > > > > > if C1 then > > > > > WState_NS <= S1; > > > > > > > > > > elsif C2 then > > > > > WState_NS <= S2; > > > > > > > > > > else > > > > > WState_NS <= S0; > > > > > end if; > > > > > ...; > > > > > end case; > > > > > end process; > > > > > > > > > > Now a synthesizer must generate a signal S0_C1 as follows > > > > > > > > > > S0_C1 <= not SINI and WState = S0 and C1; > > > > > > > > > > When S0_C1 is asserted, WState will go from S0 to S1. > > > > > > > > > > I call signal S0_C1 a jumping signal for the state machine. > > > > > > > > > > I want to know: > > > > > 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > > > > > > > > > > 2. If there is a systematic circuit structure, what its name is? > > > > > > > > > > 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > > > > > > > First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. > > > > > > > > I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. > > > > > > > > There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? > > > > > > > > Does this make sense? > > > > > > > > Rick C. > > > > > > > > Tesla referral code + https://ts.la/richard11209 > > > > > > Opps, I should have said if "the state variable WState_NS is two bits" > > > > > > Rick C. > > > > Rick, > > How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. > > > > S0_C1 logic is A BIT SIGNAL. > > That is where you fail to understand. Your code does not include the signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any design tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > > So if you only wish to suppose that the signal S0_C1 exists in your theoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > > Of your questions: > > I want to know: > > 1. Is there a systematic circuit structure or a systematic method that can > generate signal S0_C1 and others. I think it is an oldest circuit. > > Yes, it is called a state/next-state table and is very simple. > > > 2. If there is a systematic circuit structure, what its name is? > > We just call it "logic". > > > 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > Yes, they take the logic you define in your HDL and apply the many types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design. > > Rick C. > > Tesla referral code -- https://ts.la/richard11209Hi Rick, I don't want to start an argument about what I am doing, right or wrong. In a month or so I will publish something that will show your following 2 claims are wrong: 1. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. 2. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. Thank you. Weng
Reply by ●December 15, 20182018-12-15
On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote:> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com wrote: > > On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: > > > On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote: > > > > On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: > > > > > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > > > > > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > > > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > > > > > Hi, > > > > > > > > > > > > > > > > What is the name of the circuit structure that generates a state machine's jumping signals? > > > > > > > > > > > > > > > > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > > > > > > > > > > > > > > > What is the correct name? > > > > > > > > > > > > > > > > Thank you. > > > > > > > > > > > > > > > > Weng > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Transition or next state logic? > > > > > > > > > > > > > > Hans > > > > > > > www.ht-lab.com > > > > > > > > > > > > Hi, > > > > > > > > > > > > Sorry, maybe I did not specify my question clearly. > > > > > > > > > > > > Here is a code example I would ask for answer: > > > > > > > > > > > > type State_Type is ( > > > > > > S0, S1, ...); > > > > > > > > > > > > signal WState, WState_NS : State_Type; > > > > > > ...; > > > > > > > > > > > > a : process(CLK) > > > > > > begin > > > > > > if rising_edge(CLK) then > > > > > > if SINI = '1' then > > > > > > WState <= S0; > > > > > > > > > > > > else > > > > > > WState <= WState_NS; > > > > > > end if; > > > > > > end if; > > > > > > end process; > > > > > > > > > > > > b : process(all) > > > > > > begin > > > > > > case WState is > > > > > > when S0 => > > > > > > if C1 then > > > > > > WState_NS <= S1; > > > > > > > > > > > > elsif C2 then > > > > > > WState_NS <= S2; > > > > > > > > > > > > else > > > > > > WState_NS <= S0; > > > > > > end if; > > > > > > ...; > > > > > > end case; > > > > > > end process; > > > > > > > > > > > > Now a synthesizer must generate a signal S0_C1 as follows > > > > > > > > > > > > S0_C1 <= not SINI and WState = S0 and C1; > > > > > > > > > > > > When S0_C1 is asserted, WState will go from S0 to S1. > > > > > > > > > > > > I call signal S0_C1 a jumping signal for the state machine. > > > > > > > > > > > > I want to know: > > > > > > 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > > > > > > > > > > > > 2. If there is a systematic circuit structure, what its name is? > > > > > > > > > > > > 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > > > > > > > > > First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. > > > > > > > > > > I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. > > > > > > > > > > There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? > > > > > > > > > > Does this make sense? > > > > > > > > > > Rick C. > > > > > > > > > > Tesla referral code + https://ts.la/richard11209 > > > > > > > > Opps, I should have said if "the state variable WState_NS is two bits" > > > > > > > > Rick C. > > > > > > Rick, > > > How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. > > > > > > S0_C1 logic is A BIT SIGNAL. > > > > That is where you fail to understand. Your code does not include the signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any design tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > > > > So if you only wish to suppose that the signal S0_C1 exists in your theoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > > > > Of your questions: > > > I want to know: > > > 1. Is there a systematic circuit structure or a systematic method that can > generate signal S0_C1 and others. I think it is an oldest circuit. > > > > Yes, it is called a state/next-state table and is very simple. > > > > > 2. If there is a systematic circuit structure, what its name is? > > > > We just call it "logic". > > > > > 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > > > Yes, they take the logic you define in your HDL and apply the many types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design. > > > > Rick C. > > > > Tesla referral code -- https://ts.la/richard11209 > > Hi Rick, > I don't want to start an argument about what I am doing, right or wrong. In a month or so I will publish something that will show your following 2 claims are wrong: > > 1. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > > 2. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine.No need to argue. Just explain. "The best argument is that which seems merely an explanation." - Dale Carnegie I have studied the 1-hot state machine. The only signal required for each "hot" (state element) is it's next value. That value depends on *all* the possible transitions into a given state, not just a transition from any one state into that state which is what your S0_C1 bit signal is. The actual signal at the input to the state FF is the logical OR of the equivalent signal for transitions from *all* the states that have transitions into this state, including a transition from this state itself... unless the clock enable is also used, sometimes inefficiently. So the input to the FF might be an OR of S0_C1, S1_C1N, S2_something... Of course, you can write your code that way if you wish (write code, draw diagrams, etc). My only point is this has nothing to do with the actual resulting signals produced to construct the state machine in an FPGA or other logic device. The actual input to the state FF is what we call next_state and is not always equivalent to what you seem to be picturing. What you seem to be picturing can be used in design, but it may not be a real signal in the implementation. Rick C. Tesla referral code -+ https://ts.la/richard11209
