On 15/12/2018 07:50, gnuarm.deletethisbit@gmail.com wrote:> On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote: >> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com wrote: >>> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: >>>> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote: >>>>> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: >>>>>> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: >>>>>>> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: >>>>>>>> On 13/12/2018 13:45, Weng Tianxiang wrote: >>>>>>>>> Hi, >>>>>>>>> >>>>>>>>> What is the name of the circuit structure that generates a state machine's jumping signals? >>>>>>>>> >>>>>>>>> I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. >>>>>>>>> >>>>>>>>> What is the correct name? >>>>>>>>> >>>>>>>>> Thank you. >>>>>>>>> >>>>>>>>> Weng >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>> Transition or next state logic? >>>>>>>> >>>>>>>> Hans >>>>>>>> www.ht-lab.com >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> Sorry, maybe I did not specify my question clearly. >>>>>>> >>>>>>> Here is a code example I would ask for answer: >>>>>>> >>>>>>> type State_Type is ( >>>>>>> S0, S1, ...); >>>>>>> >>>>>>> signal WState, WState_NS : State_Type; >>>>>>> ...; >>>>>>> >>>>>>> a : process(CLK) >>>>>>> begin >>>>>>> if rising_edge(CLK) then >>>>>>> if SINI = '1' then >>>>>>> WState <= S0; >>>>>>> >>>>>>> else >>>>>>> WState <= WState_NS; >>>>>>> end if; >>>>>>> end if; >>>>>>> end process; >>>>>>> >>>>>>> b : process(all) >>>>>>> begin >>>>>>> case WState is >>>>>>> when S0 => >>>>>>> if C1 then >>>>>>> WState_NS <= S1; >>>>>>> >>>>>>> elsif C2 then >>>>>>> WState_NS <= S2; >>>>>>> >>>>>>> else >>>>>>> WState_NS <= S0; >>>>>>> end if; >>>>>>> ...; >>>>>>> end case; >>>>>>> end process; >>>>>>> >>>>>>> Now a synthesizer must generate a signal S0_C1 as follows >>>>>>> >>>>>>> S0_C1 <= not SINI and WState = S0 and C1; >>>>>>> >>>>>>> When S0_C1 is asserted, WState will go from S0 to S1. >>>>>>> >>>>>>> I call signal S0_C1 a jumping signal for the state machine. >>>>>>> >>>>>>> I want to know: >>>>>>> 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. >>>>>>> >>>>>>> 2. If there is a systematic circuit structure, what its name is? >>>>>>> >>>>>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? >>>>>> >>>>>> First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. >>>>>> >>>>>> I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. >>>>>> >>>>>> There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? >>>>>> >>>>>> Does this make sense? >>>>>> >>>>>> Rick C. >>>>>> >>>>>> Tesla referral code + https://ts.la/richard11209 >>>>> >>>>> Opps, I should have said if "the state variable WState_NS is two bits" >>>>> >>>>> Rick C. >>>> >>>> Rick, >>>> How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. >>>> >>>> S0_C1 logic is A BIT SIGNAL. >>> >>> That is where you fail to understand. Your code does not include the signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any design tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. >>> >>> So if you only wish to suppose that the signal S0_C1 exists in your theoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. >>> >>> Of your questions: >>>> I want to know: >>>> 1. Is there a systematic circuit structure or a systematic method that can > generate signal S0_C1 and others. I think it is an oldest circuit. >>> >>> Yes, it is called a state/next-state table and is very simple. >>> >>>> 2. If there is a systematic circuit structure, what its name is? >>> >>> We just call it "logic". >>> >>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? >>> >>> Yes, they take the logic you define in your HDL and apply the many types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design. >>> >>> Rick C. >>> >>> Tesla referral code -- https://ts.la/richard11209 >> >> Hi Rick, >> I don't want to start an argument about what I am doing, right or wrong. In a month or so I will publish something that will show your following 2 claims are wrong: >> >> 1. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. >> >> 2. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > > No need to argue. Just explain. "The best argument is that which seems merely an explanation." - Dale Carnegie > > I have studied the 1-hot state machine. The only signal required for each "hot" (state element) is it's next value. That value depends on *all* the possible transitions into a given state, not just a transition from any one state into that state which is what your S0_C1 bit signal is. The actual signal at the input to the state FF is the logical OR of the equivalent signal for transitions from *all* the states that have transitions into this state, including a transition from this state itself... unless the clock enable is also used, sometimes inefficiently. So the input to the FF might be an OR of S0_C1, S1_C1N, S2_something... > > Of course, you can write your code that way if you wish (write code, draw diagrams, etc). My only point is this has nothing to do with the actual resulting signals produced to construct the state machine in an FPGA or other logic device. The actual input to the state FF is what we call next_state and is not always equivalent to what you seem to be picturing. What you seem to be picturing can be used in design, but it may not be a real signal in the implementation. > > Rick C. > > Tesla referral code -+ https://ts.la/richard11209 >In Xilinx can't you looks at the RTL logic generated and see what signals are being produced? Dave
What is the name of the circuit structure that generates a state machine's jumping signals?
Started by ●December 13, 2018
Reply by ●December 15, 20182018-12-15
Reply by ●December 15, 20182018-12-15
On Saturday, December 15, 2018 at 3:50:42 AM UTC-5, David Wade wrote:> On 15/12/2018 07:50, gnuarm.deletethisbit@gmail.com wrote: > > On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote: > >> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com wrote: > >>> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: > >>>> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote: > >>>>> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: > >>>>>> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > >>>>>>> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > >>>>>>>> On 13/12/2018 13:45, Weng Tianxiang wrote: > >>>>>>>>> Hi, > >>>>>>>>> > >>>>>>>>> What is the name of the circuit structure that generates a state machine's jumping signals? > >>>>>>>>> > >>>>>>>>> I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > >>>>>>>>> > >>>>>>>>> What is the correct name? > >>>>>>>>> > >>>>>>>>> Thank you. > >>>>>>>>> > >>>>>>>>> Weng > >>>>>>>>> > >>>>>>>>> > >>>>>>>>> > >>>>>>>> Transition or next state logic? > >>>>>>>> > >>>>>>>> Hans > >>>>>>>> www.ht-lab.com > >>>>>>> > >>>>>>> Hi, > >>>>>>> > >>>>>>> Sorry, maybe I did not specify my question clearly. > >>>>>>> > >>>>>>> Here is a code example I would ask for answer: > >>>>>>> > >>>>>>> type State_Type is ( > >>>>>>> S0, S1, ...); > >>>>>>> > >>>>>>> signal WState, WState_NS : State_Type; > >>>>>>> ...; > >>>>>>> > >>>>>>> a : process(CLK) > >>>>>>> begin > >>>>>>> if rising_edge(CLK) then > >>>>>>> if SINI = '1' then > >>>>>>> WState <= S0; > >>>>>>> > >>>>>>> else > >>>>>>> WState <= WState_NS; > >>>>>>> end if; > >>>>>>> end if; > >>>>>>> end process; > >>>>>>> > >>>>>>> b : process(all) > >>>>>>> begin > >>>>>>> case WState is > >>>>>>> when S0 => > >>>>>>> if C1 then > >>>>>>> WState_NS <= S1; > >>>>>>> > >>>>>>> elsif C2 then > >>>>>>> WState_NS <= S2; > >>>>>>> > >>>>>>> else > >>>>>>> WState_NS <= S0; > >>>>>>> end if; > >>>>>>> ...; > >>>>>>> end case; > >>>>>>> end process; > >>>>>>> > >>>>>>> Now a synthesizer must generate a signal S0_C1 as follows > >>>>>>> > >>>>>>> S0_C1 <= not SINI and WState = S0 and C1; > >>>>>>> > >>>>>>> When S0_C1 is asserted, WState will go from S0 to S1. > >>>>>>> > >>>>>>> I call signal S0_C1 a jumping signal for the state machine. > >>>>>>> > >>>>>>> I want to know: > >>>>>>> 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > >>>>>>> > >>>>>>> 2. If there is a systematic circuit structure, what its name is? > >>>>>>> > >>>>>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > >>>>>> > >>>>>> First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. > >>>>>> > >>>>>> I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. > >>>>>> > >>>>>> There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? > >>>>>> > >>>>>> Does this make sense? > >>>>>> > >>>>>> Rick C. > >>>>>> > >>>>>> Tesla referral code + https://ts.la/richard11209 > >>>>> > >>>>> Opps, I should have said if "the state variable WState_NS is two bits" > >>>>> > >>>>> Rick C. > >>>> > >>>> Rick, > >>>> How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. > >>>> > >>>> S0_C1 logic is A BIT SIGNAL. > >>> > >>> That is where you fail to understand. Your code does not include the signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any design tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > >>> > >>> So if you only wish to suppose that the signal S0_C1 exists in your theoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > >>> > >>> Of your questions: > >>>> I want to know: > >>>> 1. Is there a systematic circuit structure or a systematic method that can > generate signal S0_C1 and others. I think it is an oldest circuit. > >>> > >>> Yes, it is called a state/next-state table and is very simple. > >>> > >>>> 2. If there is a systematic circuit structure, what its name is? > >>> > >>> We just call it "logic". > >>> > >>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > >>> > >>> Yes, they take the logic you define in your HDL and apply the many types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design. > >>> > >>> Rick C. > >>> > >>> Tesla referral code -- https://ts.la/richard11209 > >> > >> Hi Rick, > >> I don't want to start an argument about what I am doing, right or wrong. In a month or so I will publish something that will show your following 2 claims are wrong: > >> > >> 1. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > >> > >> 2. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > > > > No need to argue. Just explain. "The best argument is that which seems merely an explanation." - Dale Carnegie > > > > I have studied the 1-hot state machine. The only signal required for each "hot" (state element) is it's next value. That value depends on *all* the possible transitions into a given state, not just a transition from any one state into that state which is what your S0_C1 bit signal is. The actual signal at the input to the state FF is the logical OR of the equivalent signal for transitions from *all* the states that have transitions into this state, including a transition from this state itself... unless the clock enable is also used, sometimes inefficiently. So the input to the FF might be an OR of S0_C1, S1_C1N, S2_something... > > > > Of course, you can write your code that way if you wish (write code, draw diagrams, etc). My only point is this has nothing to do with the actual resulting signals produced to construct the state machine in an FPGA or other logic device. The actual input to the state FF is what we call next_state and is not always equivalent to what you seem to be picturing. What you seem to be picturing can be used in design, but it may not be a real signal in the implementation. > > > > Rick C. > > > > Tesla referral code -+ https://ts.la/richard11209 > > > > In Xilinx can't you looks at the RTL logic generated and see what > signals are being produced?Sure, go for it. Have you ever done it? There are times when I know what logic I want in terms of the elements in the FPGA. Trying to get the tool to produce that logic can actually be hard. I'm not sure if Weng thinks the tools will produce exactly what he is thinking or if he is thinking the signals he is talking about are somehow fundamental to the nature of a state machine. He won't say, likely because he thinks there is something to be patented there. Yeah, he may get a patent, but it's not like it will be useful. I think he was the guy who came up with some fantastic idea of how to design wave pipeline architectures. We tried to explain to him that he appeared to be oversimplifying the matter and that time delay variance must be considered when constructing such designs. He says he'll be back in a couple of months when he has his patent applied for and he can discuss the details. Rick C. Tesla referral code +- https://ts.la/richard11209 Get 6 months of free supercharging
Reply by ●December 15, 20182018-12-15
On Saturday, December 15, 2018 at 12:50:42 AM UTC-8, David Wade wrote:> On 15/12/2018 07:50, gnuarm.deletethisbit@gmail.com wrote: > > On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote: > >> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com wrote: > >>> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: > >>>> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote: > >>>>> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: > >>>>>> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > >>>>>>> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > >>>>>>>> On 13/12/2018 13:45, Weng Tianxiang wrote: > >>>>>>>>> Hi, > >>>>>>>>> > >>>>>>>>> What is the name of the circuit structure that generates a state machine's jumping signals? > >>>>>>>>> > >>>>>>>>> I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > >>>>>>>>> > >>>>>>>>> What is the correct name? > >>>>>>>>> > >>>>>>>>> Thank you. > >>>>>>>>> > >>>>>>>>> Weng > >>>>>>>>> > >>>>>>>>> > >>>>>>>>> > >>>>>>>> Transition or next state logic? > >>>>>>>> > >>>>>>>> Hans > >>>>>>>> www.ht-lab.com > >>>>>>> > >>>>>>> Hi, > >>>>>>> > >>>>>>> Sorry, maybe I did not specify my question clearly. > >>>>>>> > >>>>>>> Here is a code example I would ask for answer: > >>>>>>> > >>>>>>> type State_Type is ( > >>>>>>> S0, S1, ...); > >>>>>>> > >>>>>>> signal WState, WState_NS : State_Type; > >>>>>>> ...; > >>>>>>> > >>>>>>> a : process(CLK) > >>>>>>> begin > >>>>>>> if rising_edge(CLK) then > >>>>>>> if SINI = '1' then > >>>>>>> WState <= S0; > >>>>>>> > >>>>>>> else > >>>>>>> WState <= WState_NS; > >>>>>>> end if; > >>>>>>> end if; > >>>>>>> end process; > >>>>>>> > >>>>>>> b : process(all) > >>>>>>> begin > >>>>>>> case WState is > >>>>>>> when S0 => > >>>>>>> if C1 then > >>>>>>> WState_NS <= S1; > >>>>>>> > >>>>>>> elsif C2 then > >>>>>>> WState_NS <= S2; > >>>>>>> > >>>>>>> else > >>>>>>> WState_NS <= S0; > >>>>>>> end if; > >>>>>>> ...; > >>>>>>> end case; > >>>>>>> end process; > >>>>>>> > >>>>>>> Now a synthesizer must generate a signal S0_C1 as follows > >>>>>>> > >>>>>>> S0_C1 <= not SINI and WState = S0 and C1; > >>>>>>> > >>>>>>> When S0_C1 is asserted, WState will go from S0 to S1. > >>>>>>> > >>>>>>> I call signal S0_C1 a jumping signal for the state machine. > >>>>>>> > >>>>>>> I want to know: > >>>>>>> 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > >>>>>>> > >>>>>>> 2. If there is a systematic circuit structure, what its name is? > >>>>>>> > >>>>>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > >>>>>> > >>>>>> First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. > >>>>>> > >>>>>> I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. > >>>>>> > >>>>>> There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? > >>>>>> > >>>>>> Does this make sense? > >>>>>> > >>>>>> Rick C. > >>>>>> > >>>>>> Tesla referral code + https://ts.la/richard11209 > >>>>> > >>>>> Opps, I should have said if "the state variable WState_NS is two bits" > >>>>> > >>>>> Rick C. > >>>> > >>>> Rick, > >>>> How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. > >>>> > >>>> S0_C1 logic is A BIT SIGNAL. > >>> > >>> That is where you fail to understand. Your code does not include the signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any design tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > >>> > >>> So if you only wish to suppose that the signal S0_C1 exists in your theoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > >>> > >>> Of your questions: > >>>> I want to know: > >>>> 1. Is there a systematic circuit structure or a systematic method that can > generate signal S0_C1 and others. I think it is an oldest circuit. > >>> > >>> Yes, it is called a state/next-state table and is very simple. > >>> > >>>> 2. If there is a systematic circuit structure, what its name is? > >>> > >>> We just call it "logic". > >>> > >>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > >>> > >>> Yes, they take the logic you define in your HDL and apply the many types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design. > >>> > >>> Rick C. > >>> > >>> Tesla referral code -- https://ts.la/richard11209 > >> > >> Hi Rick, > >> I don't want to start an argument about what I am doing, right or wrong. In a month or so I will publish something that will show your following 2 claims are wrong: > >> > >> 1. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > >> > >> 2. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > > > > No need to argue. Just explain. "The best argument is that which seems merely an explanation." - Dale Carnegie > > > > I have studied the 1-hot state machine. The only signal required for each "hot" (state element) is it's next value. That value depends on *all* the possible transitions into a given state, not just a transition from any one state into that state which is what your S0_C1 bit signal is. The actual signal at the input to the state FF is the logical OR of the equivalent signal for transitions from *all* the states that have transitions into this state, including a transition from this state itself... unless the clock enable is also used, sometimes inefficiently. So the input to the FF might be an OR of S0_C1, S1_C1N, S2_something... > > > > Of course, you can write your code that way if you wish (write code, draw diagrams, etc). My only point is this has nothing to do with the actual resulting signals produced to construct the state machine in an FPGA or other logic device. The actual input to the state FF is what we call next_state and is not always equivalent to what you seem to be picturing. What you seem to be picturing can be used in design, but it may not be a real signal in the implementation. > > > > Rick C. > > > > Tesla referral code -+ https://ts.la/richard11209 > > > > In Xilinx can't you looks at the RTL logic generated and see what > signals are being produced? > > DaveRick, We don't have to argue, follow Dave's advice, take my code, compile it in Xilinx, look at the generated logic, you would find my S0_C1 signal is there, whether you have 10 states or 100 states. Very simple thing can be solved by Dave's advice and facts, not by argument. I have spent a lot of time reading the generated logic! Weng
Reply by ●December 15, 20182018-12-15
On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wrote:> On Saturday, December 15, 2018 at 12:50:42 AM UTC-8, David Wade wrote: > > On 15/12/2018 07:50, gnuarm.deletethisbit@gmail.com wrote: > > > On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote: > > >> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com wrote: > > >>> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: > > >>>> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote: > > >>>>> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: > > >>>>>> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > > >>>>>>> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > >>>>>>>> On 13/12/2018 13:45, Weng Tianxiang wrote: > > >>>>>>>>> Hi, > > >>>>>>>>> > > >>>>>>>>> What is the name of the circuit structure that generates a state machine's jumping signals? > > >>>>>>>>> > > >>>>>>>>> I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. > > >>>>>>>>> > > >>>>>>>>> What is the correct name? > > >>>>>>>>> > > >>>>>>>>> Thank you. > > >>>>>>>>> > > >>>>>>>>> Weng > > >>>>>>>>> > > >>>>>>>>> > > >>>>>>>>> > > >>>>>>>> Transition or next state logic? > > >>>>>>>> > > >>>>>>>> Hans > > >>>>>>>> www.ht-lab.com > > >>>>>>> > > >>>>>>> Hi, > > >>>>>>> > > >>>>>>> Sorry, maybe I did not specify my question clearly. > > >>>>>>> > > >>>>>>> Here is a code example I would ask for answer: > > >>>>>>> > > >>>>>>> type State_Type is ( > > >>>>>>> S0, S1, ...); > > >>>>>>> > > >>>>>>> signal WState, WState_NS : State_Type; > > >>>>>>> ...; > > >>>>>>> > > >>>>>>> a : process(CLK) > > >>>>>>> begin > > >>>>>>> if rising_edge(CLK) then > > >>>>>>> if SINI = '1' then > > >>>>>>> WState <= S0; > > >>>>>>> > > >>>>>>> else > > >>>>>>> WState <= WState_NS; > > >>>>>>> end if; > > >>>>>>> end if; > > >>>>>>> end process; > > >>>>>>> > > >>>>>>> b : process(all) > > >>>>>>> begin > > >>>>>>> case WState is > > >>>>>>> when S0 => > > >>>>>>> if C1 then > > >>>>>>> WState_NS <= S1; > > >>>>>>> > > >>>>>>> elsif C2 then > > >>>>>>> WState_NS <= S2; > > >>>>>>> > > >>>>>>> else > > >>>>>>> WState_NS <= S0; > > >>>>>>> end if; > > >>>>>>> ...; > > >>>>>>> end case; > > >>>>>>> end process; > > >>>>>>> > > >>>>>>> Now a synthesizer must generate a signal S0_C1 as follows > > >>>>>>> > > >>>>>>> S0_C1 <= not SINI and WState = S0 and C1; > > >>>>>>> > > >>>>>>> When S0_C1 is asserted, WState will go from S0 to S1. > > >>>>>>> > > >>>>>>> I call signal S0_C1 a jumping signal for the state machine. > > >>>>>>> > > >>>>>>> I want to know: > > >>>>>>> 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > > >>>>>>> > > >>>>>>> 2. If there is a systematic circuit structure, what its name is? > > >>>>>>> > > >>>>>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > >>>>>> > > >>>>>> First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. > > >>>>>> > > >>>>>> I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. > > >>>>>> > > >>>>>> There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? > > >>>>>> > > >>>>>> Does this make sense? > > >>>>>> > > >>>>>> Rick C. > > >>>>>> > > >>>>>> Tesla referral code + https://ts.la/richard11209 > > >>>>> > > >>>>> Opps, I should have said if "the state variable WState_NS is two bits" > > >>>>> > > >>>>> Rick C. > > >>>> > > >>>> Rick, > > >>>> How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. > > >>>> > > >>>> S0_C1 logic is A BIT SIGNAL. > > >>> > > >>> That is where you fail to understand. Your code does not include the signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any design tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > > >>> > > >>> So if you only wish to suppose that the signal S0_C1 exists in your theoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > > >>> > > >>> Of your questions: > > >>>> I want to know: > > >>>> 1. Is there a systematic circuit structure or a systematic method that can > generate signal S0_C1 and others. I think it is an oldest circuit. > > >>> > > >>> Yes, it is called a state/next-state table and is very simple. > > >>> > > >>>> 2. If there is a systematic circuit structure, what its name is? > > >>> > > >>> We just call it "logic". > > >>> > > >>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > >>> > > >>> Yes, they take the logic you define in your HDL and apply the many types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design. > > >>> > > >>> Rick C. > > >>> > > >>> Tesla referral code -- https://ts.la/richard11209 > > >> > > >> Hi Rick, > > >> I don't want to start an argument about what I am doing, right or wrong. In a month or so I will publish something that will show your following 2 claims are wrong: > > >> > > >> 1. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. > > >> > > >> 2. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > > > > > > No need to argue. Just explain. "The best argument is that which seems merely an explanation." - Dale Carnegie > > > > > > I have studied the 1-hot state machine. The only signal required for each "hot" (state element) is it's next value. That value depends on *all* the possible transitions into a given state, not just a transition from any one state into that state which is what your S0_C1 bit signal is. The actual signal at the input to the state FF is the logical OR of the equivalent signal for transitions from *all* the states that have transitions into this state, including a transition from this state itself... unless the clock enable is also used, sometimes inefficiently. So the input to the FF might be an OR of S0_C1, S1_C1N, S2_something... > > > > > > Of course, you can write your code that way if you wish (write code, draw diagrams, etc). My only point is this has nothing to do with the actual resulting signals produced to construct the state machine in an FPGA or other logic device. The actual input to the state FF is what we call next_state and is not always equivalent to what you seem to be picturing. What you seem to be picturing can be used in design, but it may not be a real signal in the implementation. > > > > > > Rick C. > > > > > > Tesla referral code -+ https://ts.la/richard11209 > > > > > > > In Xilinx can't you looks at the RTL logic generated and see what > > signals are being produced? > > > > Dave > > Rick, > > We don't have to argue, follow Dave's advice, take my code, compile it in Xilinx, look at the generated logic, you would find my S0_C1 signal is there, whether you have 10 states or 100 states. > > Very simple thing can be solved by Dave's advice and facts, not by argument. > > I have spent a lot of time reading the generated logic!Where would I find your signal? This is your design, your claim. Have you synthesized the program (it won't compile as it is not complete). else WState_NS <= S0; end if; ...; end case; There is a lot assumed when you typed the "..." The fact remains that in the general case the only signal that is assured to exist in the implementation is the "next state" signal because it is the input to the FF. In certain cases the "next state" signal will be the same as your S0_C1 signal, but not in general. It doesn't matter what the trial cases you have analyzed show. You can't prove a general rule by examining a few specific cases. You keep referring to this as "argument". I don't understand. Is all discussion with you an argument? Rick C. Tesla referral code ++ https://ts.la/richard11209 Get 6 months of free supercharging
Reply by ●December 15, 20182018-12-15
On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wrote:>=20 > We don't have to argue, follow Dave's advice, take my code, compile it in=Xilinx, look at the generated logic, you would find my S0_C1 signal is the= re, whether you have 10 states or 100 states.=20>=20Take that same code and compile it in Quartus and you will find no such S0_= C1 signal. Instead what you will see is a flip flop to hold WState.S0 with= the 'D' input coming from lookup table logic. The output of the lookup is= the next state of WState.S0. That lookup table takes as input four signal= s: C1, Sini, WState.S0 and C2. The lookup table implements the following = logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic imp= lemented in the entire post-fit design. In your earlier code posting you stated: Now a synthesizer must generate a= signal S0_C1 as follows: S0_C1 <=3D not SINI and WState =3D S0 and C1;=20 Using Quartus, there is no individual signal for the state transition to S0= from input C1 as you have stated seeing when using Xilinx. If Xilinx gene= rates such a signal as you say, then it is doing so very inefficiently sinc= e, in order to generate the final next state input to the flip flop, there = must be additional logic that you did not mention which will create additio= nal delay and therefore lower performance. I find it hard to believe that = a big brand like Xilinx would synthesize something as simple as you posted = so poorly. If it really does do as you say, then I'm even happier to be a = user of Quartus rather than Xilinx...but again, I still highly doubt that b= rand X is that bad. Quartus offers several netlist views: RTL Viewer, State Machine, post-mapp= ing, and post-fitting. My description above is based on the post-fitting v= iew, but none of the other views show a discrete signal to handle the trans= ition of S0 based on input C1.> Very simple thing can be solved by Dave's advice and facts, not by argume=nt.=20>=20I agree and I've posted my full set of facts. Perhaps you can be as fully = descriptive using Xilinx tools. If what you claim to see from Xilinx is true, you seem to have left out som= e details. For example, while you say you see a signal "S0_C1 <=3D not SIN= I and WState =3D S0 and C1;" this cannot be the next state logic since it d= oes not depend on C2 and clearly your state machine does depend on C2. So = there is some additional logic that you have not mentioned for some reason.= Maybe you are discussing something from code that you haven't posted who = knows? =20 Perhaps you or someone else should run the complete design code that I have= posted below with Xilinx to either confirm or refute your claim. At least= that way we all know exactly what code is under discussion. In any case, what you claim regarding S0_C1 right now is only true for your= unposted single design when run using Xilinx tools and only when run by yo= u. That's a very narrow claim. It's already been pointed out in this thre= ad why your claim will not in general be true for: - Anything other than one-hot encoded state machine - Anything other than if the state only depends on one input - Now this post shows that it is not true with what I believe to be your co= de when run using a different synthesis tool.> I have spent a lot of time reading the generated logic! >=20That may be true, but if you have spent any time it is not evident, at leas= t not to me. Kevin --- Start of code --- library ieee; use ieee.std_logic_1164.all; entity WengState is port( Clk: in std_ulogic; Sini: in std_ulogic; C1: in std_ulogic; C2: in std_ulogic; Gazouta: out std_ulogic ); end WengState; architecture RTL of WengState is type State_Type is (S0, S1, S2);=20 signal WState, WState_NS : State_Type;=20 begin Gazouta <=3D '1' when (WState =3D S0) else '0'; a : process(CLK)=20 begin=20 if rising_edge(CLK) then=20 if SINI =3D '1' then =20 WState <=3D S0;=20 else=20 WState <=3D WState_NS;=20 end if;=20 end if;=20 end process;=20 b : process(all)=20 begin=20 WState_NS <=3D WState; -- KJ added case WState is=20 when S0 =3D>=20 if C1 then=20 WState_NS <=3D S1;=20 elsif C2 then=20 WState_NS <=3D S2;=20 =20 else =20 WState_NS <=3D S0;=20 end if; when others =3D> null; end case;=20 end process; end RTL; --- End of code ---
Reply by ●December 15, 20182018-12-15
On Saturday, December 15, 2018 at 8:49:54 AM UTC-8, KJ wrote:> On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wrote: > > > > We don't have to argue, follow Dave's advice, take my code, compile it in Xilinx, look at the generated logic, you would find my S0_C1 signal is there, whether you have 10 states or 100 states. > > > Take that same code and compile it in Quartus and you will find no such S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 with the 'D' input coming from lookup table logic. The output of the lookup is the next state of WState.S0. That lookup table takes as input four signals: C1, Sini, WState.S0 and C2. The lookup table implements the following logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic implemented in the entire post-fit design. > > In your earlier code posting you stated: Now a synthesizer must generate a signal S0_C1 as follows: S0_C1 <= not SINI and WState = S0 and C1; > > Using Quartus, there is no individual signal for the state transition to S0 from input C1 as you have stated seeing when using Xilinx. If Xilinx generates such a signal as you say, then it is doing so very inefficiently since, in order to generate the final next state input to the flip flop, there must be additional logic that you did not mention which will create additional delay and therefore lower performance. I find it hard to believe that a big brand like Xilinx would synthesize something as simple as you posted so poorly. If it really does do as you say, then I'm even happier to be a user of Quartus rather than Xilinx...but again, I still highly doubt that brand X is that bad. > > Quartus offers several netlist views: RTL Viewer, State Machine, post-mapping, and post-fitting. My description above is based on the post-fitting view, but none of the other views show a discrete signal to handle the transition of S0 based on input C1. > > > Very simple thing can be solved by Dave's advice and facts, not by argument. > > > I agree and I've posted my full set of facts. Perhaps you can be as fully descriptive using Xilinx tools. > > If what you claim to see from Xilinx is true, you seem to have left out some details. For example, while you say you see a signal "S0_C1 <= not SINI and WState = S0 and C1;" this cannot be the next state logic since it does not depend on C2 and clearly your state machine does depend on C2. So there is some additional logic that you have not mentioned for some reason. Maybe you are discussing something from code that you haven't posted who knows? > > Perhaps you or someone else should run the complete design code that I have posted below with Xilinx to either confirm or refute your claim. At least that way we all know exactly what code is under discussion. > > In any case, what you claim regarding S0_C1 right now is only true for your unposted single design when run using Xilinx tools and only when run by you. That's a very narrow claim. It's already been pointed out in this thread why your claim will not in general be true for: > - Anything other than one-hot encoded state machine > - Anything other than if the state only depends on one input > - Now this post shows that it is not true with what I believe to be your code when run using a different synthesis tool. > > > I have spent a lot of time reading the generated logic! > > > That may be true, but if you have spent any time it is not evident, at least not to me. > > Kevin > > --- Start of code --- > library ieee; > use ieee.std_logic_1164.all; > > entity WengState is > port( > Clk: in std_ulogic; > Sini: in std_ulogic; > C1: in std_ulogic; > C2: in std_ulogic; > Gazouta: out std_ulogic > ); > end WengState; > > architecture RTL of WengState is > type State_Type is (S0, S1, S2); > > signal WState, WState_NS : State_Type; > begin > Gazouta <= '1' when (WState = S0) else '0'; > > a : process(CLK) > begin > if rising_edge(CLK) then > if SINI = '1' then > WState <= S0; > > else > WState <= WState_NS; > end if; > end if; > end process; > > b : process(all) > begin > WState_NS <= WState; -- KJ added > case WState is > when S0 => > if C1 then > WState_NS <= S1; > > elsif C2 then > WState_NS <= S2; > > else > WState_NS <= S0; > end if; > when others => null; > end case; > end process; > end RTL; > --- End of code ---Hi Kevin, Thank you for your testing and you really did a very good experiment: "Take that same code and compile it in Quartus and you will find no such S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 with the 'D' input coming from lookup table logic. The output of the lookup is the next state of WState.S0. That lookup table takes as input four signals: C1, Sini, WState.S0 and C2. The lookup table implements the following logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic implemented in the entire post-fit design." 1. My signal "S0_C1 <= not SINI and WState = S0 and C1;" should be next state for state S1, not for S0!, for state S1, not for S0!, for state S1, not for S0! But you look at state S0! Please look at state S1 2. Your explanation is wrong. How do you explain LUT4 output for state S0: S0 <= not(Sini) and (C1 or C2 or WState.S0);??? Based on your explanation, when not(Sini) and (C1 = '1' or C2 = '1' or WState = S0), state S0 should be asserted on next cycle??? Based on the equation state S0 will be in state S0 forever if your explanation is correct!!@??? 3. To make the testing full, you must add something, for example, to output not Gazouta <= '1' when (WState = S0) else '0'; but WState. By optimization State S1 is cut off, because it never plays a rule, generating a logic that must be thoroughly analyzed to understand. Kevin, Thank you. Please continue! I like this type of facts, not words in argument. Weng
Reply by ●December 15, 20182018-12-15
On Saturday, December 15, 2018 at 12:56:36 PM UTC-8, Weng Tianxiang wrote:> On Saturday, December 15, 2018 at 8:49:54 AM UTC-8, KJ wrote: > > On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wrote: > > > > > > We don't have to argue, follow Dave's advice, take my code, compile it in Xilinx, look at the generated logic, you would find my S0_C1 signal is there, whether you have 10 states or 100 states. > > > > > Take that same code and compile it in Quartus and you will find no such S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 with the 'D' input coming from lookup table logic. The output of the lookup is the next state of WState.S0. That lookup table takes as input four signals: C1, Sini, WState.S0 and C2. The lookup table implements the following logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic implemented in the entire post-fit design. > > > > In your earlier code posting you stated: Now a synthesizer must generate a signal S0_C1 as follows: S0_C1 <= not SINI and WState = S0 and C1; > > > > Using Quartus, there is no individual signal for the state transition to S0 from input C1 as you have stated seeing when using Xilinx. If Xilinx generates such a signal as you say, then it is doing so very inefficiently since, in order to generate the final next state input to the flip flop, there must be additional logic that you did not mention which will create additional delay and therefore lower performance. I find it hard to believe that a big brand like Xilinx would synthesize something as simple as you posted so poorly. If it really does do as you say, then I'm even happier to be a user of Quartus rather than Xilinx...but again, I still highly doubt that brand X is that bad. > > > > Quartus offers several netlist views: RTL Viewer, State Machine, post-mapping, and post-fitting. My description above is based on the post-fitting view, but none of the other views show a discrete signal to handle the transition of S0 based on input C1. > > > > > Very simple thing can be solved by Dave's advice and facts, not by argument. > > > > > I agree and I've posted my full set of facts. Perhaps you can be as fully descriptive using Xilinx tools. > > > > If what you claim to see from Xilinx is true, you seem to have left out some details. For example, while you say you see a signal "S0_C1 <= not SINI and WState = S0 and C1;" this cannot be the next state logic since it does not depend on C2 and clearly your state machine does depend on C2. So there is some additional logic that you have not mentioned for some reason. Maybe you are discussing something from code that you haven't posted who knows? > > > > Perhaps you or someone else should run the complete design code that I have posted below with Xilinx to either confirm or refute your claim. At least that way we all know exactly what code is under discussion. > > > > In any case, what you claim regarding S0_C1 right now is only true for your unposted single design when run using Xilinx tools and only when run by you. That's a very narrow claim. It's already been pointed out in this thread why your claim will not in general be true for: > > - Anything other than one-hot encoded state machine > > - Anything other than if the state only depends on one input > > - Now this post shows that it is not true with what I believe to be your code when run using a different synthesis tool. > > > > > I have spent a lot of time reading the generated logic! > > > > > That may be true, but if you have spent any time it is not evident, at least not to me. > > > > Kevin > > > > --- Start of code --- > > library ieee; > > use ieee.std_logic_1164.all; > > > > entity WengState is > > port( > > Clk: in std_ulogic; > > Sini: in std_ulogic; > > C1: in std_ulogic; > > C2: in std_ulogic; > > Gazouta: out std_ulogic > > ); > > end WengState; > > > > architecture RTL of WengState is > > type State_Type is (S0, S1, S2); > > > > signal WState, WState_NS : State_Type; > > begin > > Gazouta <= '1' when (WState = S0) else '0'; > > > > a : process(CLK) > > begin > > if rising_edge(CLK) then > > if SINI = '1' then > > WState <= S0; > > > > else > > WState <= WState_NS; > > end if; > > end if; > > end process; > > > > b : process(all) > > begin > > WState_NS <= WState; -- KJ added > > case WState is > > when S0 => > > if C1 then > > WState_NS <= S1; > > > > elsif C2 then > > WState_NS <= S2; > > > > else > > WState_NS <= S0; > > end if; > > when others => null; > > end case; > > end process; > > end RTL; > > --- End of code --- > > Hi Kevin, > > Thank you for your testing and you really did a very good experiment: > > "Take that same code and compile it in Quartus and you will find no such S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 with the 'D' input coming from lookup table logic. The output of the lookup is the next state of WState.S0. That lookup table takes as input four signals: C1, Sini, WState.S0 and C2. The lookup table implements the following logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic implemented in the entire post-fit design." > > 1. My signal "S0_C1 <= not SINI and WState = S0 and C1;" should be next state > > for state S1, not for S0!, for state S1, not for S0!, for state S1, not for S0! > > But you look at state S0! Please look at state S1 > > 2. Your explanation is wrong. > > How do you explain LUT4 output for state S0: > > S0 <= not(Sini) and (C1 or C2 or WState.S0);??? > > Based on your explanation, when not(Sini) and (C1 = '1' or C2 = '1' or WState = S0), state S0 should be asserted on next cycle??? > > Based on the equation state S0 will be in state S0 forever if your explanation is correct!!@??? > > 3. To make the testing full, you must add something, for example, to output not Gazouta <= '1' when (WState = S0) else '0'; but WState. > > By optimization State S1 is cut off, because it never plays a rule, generating a logic that must be thoroughly analyzed to understand. > > Kevin, Thank you. Please continue! I like this type of facts, not words in argument. > > WengSorry, you must add some logic to have state S1 valid, bot being cut off. Output the state machine is not enough to keep state S1 not being cut off. Weng
Reply by ●December 16, 20182018-12-16
On Saturday, December 15, 2018 at 4:06:40 PM UTC-5, Weng Tianxiang wrote:> On Saturday, December 15, 2018 at 12:56:36 PM UTC-8, Weng Tianxiang wrote: > > On Saturday, December 15, 2018 at 8:49:54 AM UTC-8, KJ wrote: > > > On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wrote: > > > > > > > > We don't have to argue, follow Dave's advice, take my code, compile it in Xilinx, look at the generated logic, you would find my S0_C1 signal is there, whether you have 10 states or 100 states. > > > > > > > Take that same code and compile it in Quartus and you will find no such S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 with the 'D' input coming from lookup table logic. The output of the lookup is the next state of WState.S0. That lookup table takes as input four signals: C1, Sini, WState.S0 and C2. The lookup table implements the following logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic implemented in the entire post-fit design. > > > > > > In your earlier code posting you stated: Now a synthesizer must generate a signal S0_C1 as follows: S0_C1 <= not SINI and WState = S0 and C1; > > > > > > Using Quartus, there is no individual signal for the state transition to S0 from input C1 as you have stated seeing when using Xilinx. If Xilinx generates such a signal as you say, then it is doing so very inefficiently since, in order to generate the final next state input to the flip flop, there must be additional logic that you did not mention which will create additional delay and therefore lower performance. I find it hard to believe that a big brand like Xilinx would synthesize something as simple as you posted so poorly. If it really does do as you say, then I'm even happier to be a user of Quartus rather than Xilinx...but again, I still highly doubt that brand X is that bad. > > > > > > Quartus offers several netlist views: RTL Viewer, State Machine, post-mapping, and post-fitting. My description above is based on the post-fitting view, but none of the other views show a discrete signal to handle the transition of S0 based on input C1. > > > > > > > Very simple thing can be solved by Dave's advice and facts, not by argument. > > > > > > > I agree and I've posted my full set of facts. Perhaps you can be as fully descriptive using Xilinx tools. > > > > > > If what you claim to see from Xilinx is true, you seem to have left out some details. For example, while you say you see a signal "S0_C1 <= not SINI and WState = S0 and C1;" this cannot be the next state logic since it does not depend on C2 and clearly your state machine does depend on C2. So there is some additional logic that you have not mentioned for some reason. Maybe you are discussing something from code that you haven't posted who knows? > > > > > > Perhaps you or someone else should run the complete design code that I have posted below with Xilinx to either confirm or refute your claim. At least that way we all know exactly what code is under discussion. > > > > > > In any case, what you claim regarding S0_C1 right now is only true for your unposted single design when run using Xilinx tools and only when run by you. That's a very narrow claim. It's already been pointed out in this thread why your claim will not in general be true for: > > > - Anything other than one-hot encoded state machine > > > - Anything other than if the state only depends on one input > > > - Now this post shows that it is not true with what I believe to be your code when run using a different synthesis tool. > > > > > > > I have spent a lot of time reading the generated logic! > > > > > > > That may be true, but if you have spent any time it is not evident, at least not to me. > > > > > > Kevin > > > > > > --- Start of code --- > > > library ieee; > > > use ieee.std_logic_1164.all; > > > > > > entity WengState is > > > port( > > > Clk: in std_ulogic; > > > Sini: in std_ulogic; > > > C1: in std_ulogic; > > > C2: in std_ulogic; > > > Gazouta: out std_ulogic > > > ); > > > end WengState; > > > > > > architecture RTL of WengState is > > > type State_Type is (S0, S1, S2); > > > > > > signal WState, WState_NS : State_Type; > > > begin > > > Gazouta <= '1' when (WState = S0) else '0'; > > > > > > a : process(CLK) > > > begin > > > if rising_edge(CLK) then > > > if SINI = '1' then > > > WState <= S0; > > > > > > else > > > WState <= WState_NS; > > > end if; > > > end if; > > > end process; > > > > > > b : process(all) > > > begin > > > WState_NS <= WState; -- KJ added > > > case WState is > > > when S0 => > > > if C1 then > > > WState_NS <= S1; > > > > > > elsif C2 then > > > WState_NS <= S2; > > > > > > else > > > WState_NS <= S0; > > > end if; > > > when others => null; > > > end case; > > > end process; > > > end RTL; > > > --- End of code --- > > > > Hi Kevin, > > > > Thank you for your testing and you really did a very good experiment: > > > > "Take that same code and compile it in Quartus and you will find no such S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 with the 'D' input coming from lookup table logic. The output of the lookup is the next state of WState.S0. That lookup table takes as input four signals: C1, Sini, WState.S0 and C2. The lookup table implements the following logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic implemented in the entire post-fit design." > > > > 1. My signal "S0_C1 <= not SINI and WState = S0 and C1;" should be next state > > > > for state S1, not for S0!, for state S1, not for S0!, for state S1, not for S0! > > > > But you look at state S0! Please look at state S1 > > > > 2. Your explanation is wrong. > > > > How do you explain LUT4 output for state S0: > > > > S0 <= not(Sini) and (C1 or C2 or WState.S0);??? > > > > Based on your explanation, when not(Sini) and (C1 = '1' or C2 = '1' or WState = S0), state S0 should be asserted on next cycle??? > > > > Based on the equation state S0 will be in state S0 forever if your explanation is correct!!@??? > > > > 3. To make the testing full, you must add something, for example, to output not Gazouta <= '1' when (WState = S0) else '0'; but WState. > > > > By optimization State S1 is cut off, because it never plays a rule, generating a logic that must be thoroughly analyzed to understand. > > > > Kevin, Thank you. Please continue! I like this type of facts, not words in argument. > > > > Weng > > Sorry, you must add some logic to have state S1 valid, bot being cut off. Output the state machine is not enough to keep state S1 not being cut off. > > WengI have no idea what "cut off" means. The test done is not of value since it does not implement a useful state machine and not the one you described earlier. b : process(all) begin case WState is when S0 => if C1 then WState_NS <= S1; elsif C2 then WState_NS <= S2; else WState_NS <= S0; end if; ...; end case; end process; This is your code and the important part is at the end of the case code where you have "...;". This implies there is other code for the remainder of the state machine which must be added for a useful analysis. Your comment above, '1. My signal "S0_C1 <= not SINI and WState = S0 and C1;" should be next state for state S1' shows you intend your S0_C1 signal to be the next state signal of each bit of the state machine. In that case the equation will depend on *all* transitions to a given state in a 1-hot machine. If you are actually talking about the next_state equations rather than what appeared to be an intermediate signal that may or may not exist in any given design, what are your questions exactly? Rick C. Tesla referral code --- https://ts.la/richard11209 Get 6 months of free supercharging
Reply by ●December 16, 20182018-12-16
On Saturday, December 15, 2018 at 3:56:36 PM UTC-5, Weng Tianxiang wrote:> > 1. My signal "S0_C1 <= not SINI and WState = S0 and C1;" should be next state > > for state S1, not for S0!, for state S1, not for S0!, for state S1, not for S0! >Here you undercut everything that you have posted in this thread regarding your state machine. Here is why: - In your original post with your state machine, the source code showed inputs C1 and C2 that would cause a transition from state S0. Now you say "My signal "S0_C1 <= not SINI and WState = S0 and C1;" should be next state for state S1...". But if that is now the case then you've clearly shown that the code you used as the basis for your claim that signal S0_C1 MUST be generated from something different than you posted. In particular, I would wager that you added "elsif C2 then WState_NS <= S2; " after the fact and did not re-compile or re-analyze to see that the change completely undercuts what you were about to claim. Shame on you for posting code that is NOT what you used to support your (false) claim. As the group has already pointed out, your claim would only be true for a one-hot encoded, single input state machine which is exactly what you used when writing up your claim. Shame on you for not using the code that I posted to re-analyze for yourself even after I challenged you to do so. Had you done that you could have come to the realizations that I have pointed out here on your own and retracted your false claim "there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic" when all that actually gets implemented is the next state logic, nothing else.> But you look at state S0! Please look at state S1 >No reason to, your claim was about S0 and C1. Quartus implemented the inverted state S0. It then inverted that to produce the output Gazouta. I had missed the little bubble on the I/O buffer when looking at the netlist viewer. No additional logic was generated to implement since the I/O buffers can automatically generate either polarity.> 2. Your explanation is wrong. >HAHAHAHA...I presented Quartus' results for the synthesis of your state machine. Take that up with Altera/Intel, not me.> How do you explain LUT4 output for state S0: > > S0 <= not(Sini) and (C1 or C2 or WState.S0);??? > > Based on your explanation, when not(Sini) and (C1 = '1' or C2 = '1' or WState = S0), state S0 should be asserted on next cycle??? > > Based on the equation state S0 will be in state S0 forever if your explanation is correct!!@??? >See above. Quartus implemented the internal state S0 in the inverted sense.> 3. To make the testing full, you must add something, for example, to output not Gazouta <= '1' when (WState = S0) else '0'; but WState. >No, your state machine design is flawed. You posted some code for a state machine where only one state S0 is needed. Just because you think states S1 and S2 may be needed, does not mean they are. Quartus implemented your design with one state, that's on you.> By optimization State S1 is cut off, because it never plays a rule, generating a logic that must be thoroughly analyzed to understand. >Quartus did analyze that and correctly determined there is no value in state S1 or S2 and optimized them out of the fitted design. Again, you provided the state machine, not me.> Kevin, Thank you. Please continue! I like this type of facts, not words in argument. >No thanks.
Reply by ●December 16, 20182018-12-16
On Saturday, December 15, 2018 at 4:06:40 PM UTC-5, Weng Tianxiang wrote:> Sorry, you must add some logic to have state S1 valid, bot being cut off. Output the state machine is not enough to keep state S1 not being cut off. >Neither state S1 or S2 are not needed in order to implement your state machine that is functionally identical to any other implementation. Kevin
