Implementing a two-modulus PLL divider in Altera Stratix II

I am trying to use one of the enhanced PLLs in an Altera
Stratix II (EP2S60F1020C4) on the Altera DSP Development board
in order to synthesize from a 100 MHz input clock frequencies
new clock frequencies in the range 20-150 MHz. The critical
bit is: I need a frequency resolution of not more than 0.01 Hz,
which is obviously not feasible with the built-in 9-bit PLL
dividers.

I am therefore trying to build a so-called "two-modulus prescaler"
PLL. In other words, I would like to use the FPGA's internal logic
in order to build a frequency divider that toggles between
division by N and division by N-1. By adjusting the duty cycle
of the divider toggling signal, I should be able to achieve
output frequencies corresponding to high-resolution factional
frequency multiplication factors. The toggling frequency
should obviously be well above the PLL's loop filter bandwidth.
I believe I can achieve the required divisor resolution with
32-bit counters.

Question:

- Has anyone here already done something similar and may be
  able to offer advice?

- I need to feed the fbin (feed-back input) pin of the PLL from
  the internal logic (i.e., the output of my Verilog-implemented
  two-modulus divider).

  Is that possible at all in Stratix II without an external
  loop-back connection in hte PCB layout?

  In other words, can the PLL feed-back input be driven by the
  internal logic, or are these only connected via a multiplexer
  to either the PLL phase detector or (exclusive or) the internal
  logic?

- If an external feed-back connection is necessary, is there
  any better or more elegant solution than using a jumper on
  one of the extension prototype connectors of the
  Stratix II EP2S60 DSP development board?

Any other suggestions for building such a high-resolution
frequency synthesizer from a Stratix II are of course also
welcome.

Thanks for any hints!

Markus

-- 
Markus Kuhn, Computer Laboratory, University of Cambridge
http://www.cl.cam.ac.uk/~mgk25/ || CB3 0FD, Great Britain

Markus, I do not know much about Stratix PLLs   ;-)
But the traditional way to implement your function is called Direct
Digital Synthesis (DDS) aka Phase Accumulation.
You build a long ( 34 bit?) accumulator and clock it at your 100 MHz
(200 MHz would be better). The MSB is your output, and it easily has
the requested frequency resolution. It also has a max jitter of one
clock period (10 ns or 5 ns). If that is too much, you can use the PLL
to reduce it.
That's what I would do. Since the PLL's filter does not cover 0.01 Hz,
you will have some frequency wander, but that is unavoidable in your
case.
If anybody knows a trick to avoid it or reduce it, I am all ears...
Peter Alfke, Xilinx

Peter,

I used a 48 bit DDS to create a clock for telecommunications that was 
accurate to 3.5E-15.

The occasional missing clock pulse is the only issue, as that is 
instantaeneous jitter.

Either the output bits of the DDS can feed a sine look up ROM to a D/A, 
and/or you can band pass filter the clock output from the msb - or the 
D/A, or you can drive the input of a PLL with the MSB, which is in 
effect a band pass filter.

Austin

Peter Alfke wrote:

> Markus, I do not know much about Stratix PLLs   ;-)
> But the traditional way to implement your function is called Direct
> Digital Synthesis (DDS) aka Phase Accumulation.
> You build a long ( 34 bit?) accumulator and clock it at your 100 MHz
> (200 MHz would be better). The MSB is your output, and it easily has
> the requested frequency resolution. It also has a max jitter of one
> clock period (10 ns or 5 ns). If that is too much, you can use the PLL
> to reduce it.
> That's what I would do. Since the PLL's filter does not cover 0.01 Hz,
> you will have some frequency wander, but that is unavoidable in your
> case.
> If anybody knows a trick to avoid it or reduce it, I am all ears...
> Peter Alfke, Xilinx
> 

>I am therefore trying to build a so-called "two-modulus prescaler"
>PLL. In other words, I would like to use the FPGA's internal logic
>in order to build a frequency divider that toggles between
>division by N and division by N-1. By adjusting the duty cycle
>of the divider toggling signal, I should be able to achieve
>output frequencies corresponding to high-resolution factional
>frequency multiplication factors. The toggling frequency
>should obviously be well above the PLL's loop filter bandwidth.
>I believe I can achieve the required divisor resolution with
>32-bit counters.

What's the spectrum of the output of a "two-modulus prescaler"?

What's the spectrum of a DDS?

How low do I have to make the PLL bandwidth if I want to filter
out the junk?  (Assume I run the DDS output through a PLL
to filter out the steps.)

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On Mon, 20 Feb 2006 13:02:46 -0600, hmurray@suespammers.org (Hal
Murray) wrote:

>
>>I am therefore trying to build a so-called "two-modulus prescaler"
>>PLL. In other words, I would like to use the FPGA's internal logic
>>in order to build a frequency divider that toggles between
>>division by N and division by N-1. By adjusting the duty cycle
>>of the divider toggling signal, I should be able to achieve
>>output frequencies corresponding to high-resolution factional
>>frequency multiplication factors. The toggling frequency
>>should obviously be well above the PLL's loop filter bandwidth.
>>I believe I can achieve the required divisor resolution with
>>32-bit counters.
>
>What's the spectrum of the output of a "two-modulus prescaler"?
>
>What's the spectrum of a DDS?

If you're referring to the MSB of the phase accumulator, then it has
the same spectrum as the output of the dual modulus prescaler.

If implemented properly, they  will have identical outputs.

>How low do I have to make the PLL bandwidth if I want to filter
>out the junk?  (Assume I run the DDS output through a PLL
>to filter out the steps.)

That depends on the junk.  The spectrum of the junk close to the
carrier varies wildly with the ratio in the divider.  It's best to
work out the spectrum with a program.

I used to do it with a spreadsheet, but these days I use a C program
(piped into Gnuplot).

Regards,
Allan

Hal Murray wrote:
> What's the spectrum of the output of a "two-modulus prescaler"?
> 
> What's the spectrum of a DDS?
> 
> How low do I have to make the PLL bandwidth if I want to filter
> out the junk?  (Assume I run the DDS output through a PLL
> to filter out the steps.)

The output of a two-modulus prescaler (specifically "fractional-N 
synthesis") and the MSbit of a DDS (as opposed to a phase-to-sine lookup 
feeding a DAC) are the same thing - they produce the same spectra.  The 
largest spurs are related to the closest integer ratio approximations to 
the output to reference clock ratio, many smaller spurs coming from 
mixing of those components and other slightly nonlinear effects of the 
ratios that produce these beat frequencies.

With no extra help, both approaches have phase steps in some situations 
that are too low to be filtered out in an analog PLL filter.  Imagine an 
output frequency so close to a divide-by-12 that the divide-by-13 
happens once a second.  The result will be the same from the MSBit of 
the DDS and the accumulator for the divide by 12/13 control - a phase 
"slip" that has a ramp back to "steady state" controlled by the analog 
PLL filter.

The phase steps in DDS or fractional-N synthesis can be reduced by using 
the same techniques in sigma-delta converters but the control is a 
little more than a dual modulus.  If there is a phase offset from 
"ideal" that is a ramp going from -0.5 Unit Intervals (UI) phase error 
to +0.5 UI of error, adding compensation to the output divider to push 
the phase error occasionally beyond the +/- 0.5 UI range at high enough 
frequency will allow the PLL's loop filter to average the compensation 
to directly match the offest from "ideal."

Different systems have different requirements for what is "good" quality 
results.  Using the dithering just mentioned, there are often still 
noticeable spurs in the output spectrom though they won't look like much 
from the time domain.  Many systems - such as analog - can't deal with 
the associated background tones and would gladly trade off a higher 
noise floor for lower spurs.  In most of the stuff I want to deal with, 
I'm concerned about the time domain.