I have implemented a 8-bit synchronous counter by VHDL. The result is that the LED display show continuously running the count from 0 to F(in Hex). Now, I need to change the result which the LED display can count from 0 to 9 only. How can I change in the VHDL code? Can anyone answer me? Thanks a lot!! The following VHDL code are about 8-bit synchronous counter: Library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; ENTITY counter_eg IS PORT( PB1, clk_25MHz : IN std_logic; led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); END counter_eg; ARCHITECTURE c OF counter_eg IS COMPONENT counter PORT( Clock, Reset : IN std_logic; count : OUT std_logic_vector(3 DOWNTO 0)); END COMPONENT; COMPONENT dec_7seg PORT( hex_digit : IN std_logic_vector(3 DOWNTO 0); segment_a, segment_b, segment_c, segment_d, segment_e, segment_f, segment_g : OUT std_logic); END COMPONENT; COMPONENT clk_div PORT( clock_25MHz : IN std_logic; clock_1MHz : OUT std_logic; clock_100KHz : OUT std_logic; clock_10KHz : OUT std_logic; clock_1KHz : OUT std_logic; clock_100Hz : OUT std_logic; clock_10Hz : OUT std_logic; clock_1Hz : OUT std_logic); END COMPONENT; SIGNAL count : std_logic_vector(3 DOWNTO 0); SIGNAL clk_1KHz : std_logic; BEGIN c0: clk_div port map (clock_25MHz=> clk_25MHz, clock_1KHz=>clk_1KHz); c1: counter port map (clock=>clk_1KHz, reset=>PB1, count=> count); c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, led6); END c;
Questions about counter in VHDL
Started by ●March 7, 2006
Reply by ●March 7, 20062006-03-07
sandypure@yahoo.com wrote:> I have implemented a 8-bit synchronous counter by VHDL. The result is > that the LED display show continuously running the count from 0 to > F(in Hex). Now, I need to change the result which the LED display can > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > answer me? Thanks a lot!! > The following VHDL code are about 8-bit synchronous counter: > Library IEEE; > USE IEEE.std_logic_1164.all; > USE IEEE.std_logic_arith.all; > USE IEEE.std_logic_unsigned.all; > > ENTITY counter_eg IS > PORT( > PB1, clk_25MHz : IN std_logic; > led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); > END counter_eg; > > ARCHITECTURE c OF counter_eg IS > > COMPONENT counter > PORT( > Clock, Reset : IN std_logic; > count : OUT std_logic_vector(3 DOWNTO 0)); > > END COMPONENT; > > COMPONENT dec_7seg > PORT( > hex_digit : IN std_logic_vector(3 DOWNTO 0); > segment_a, segment_b, segment_c, segment_d, segment_e, > segment_f, segment_g : OUT std_logic); > END COMPONENT; > > COMPONENT clk_div > PORT( > clock_25MHz : IN std_logic; > clock_1MHz : OUT std_logic; > clock_100KHz : OUT std_logic; > clock_10KHz : OUT std_logic; > clock_1KHz : OUT std_logic; > clock_100Hz : OUT std_logic; > clock_10Hz : OUT std_logic; > clock_1Hz : OUT std_logic); > END COMPONENT; > > SIGNAL count : std_logic_vector(3 DOWNTO 0); > SIGNAL clk_1KHz : std_logic; > BEGIN > c0: clk_div port map (clock_25MHz=> clk_25MHz, clock_1KHz=>clk_1KHz); > c1: counter port map (clock=>clk_1KHz, reset=>PB1, count=> count); > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, > led6); > > END c; >I'm not going to do your homework for you but here's a suggestion, how about decoding when the count equals 9 and using this to reset your counter. For your percentage I'm sure you can figure out how to code that in your vhdl. Alan
Reply by ●March 7, 20062006-03-07
sandypure@yahoo.com wrote:> I have implemented a 8-bit synchronous counter by VHDL.I'll give you a hint, the counter is not in this file, only the intantiation of the counter. but you can decode count=10 and trigger a reset. (in this file) as Alan just said. Aurash The result is> that the LED display show continuously running the count from 0 to > F(in Hex). Now, I need to change the result which the LED display can > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > answer me? Thanks a lot!! > The following VHDL code are about 8-bit synchronous counter: > Library IEEE; > USE IEEE.std_logic_1164.all; > USE IEEE.std_logic_arith.all; > USE IEEE.std_logic_unsigned.all; > > ENTITY counter_eg IS > PORT( > PB1, clk_25MHz : IN std_logic; > led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); > END counter_eg; > > ARCHITECTURE c OF counter_eg IS > > COMPONENT counter > PORT( > Clock, Reset : IN std_logic; > count : OUT std_logic_vector(3 DOWNTO 0)); > > END COMPONENT; > > COMPONENT dec_7seg > PORT( > hex_digit : IN std_logic_vector(3 DOWNTO 0); > segment_a, segment_b, segment_c, segment_d, segment_e, > segment_f, segment_g : OUT std_logic); > END COMPONENT; > > COMPONENT clk_div > PORT( > clock_25MHz : IN std_logic; > clock_1MHz : OUT std_logic; > clock_100KHz : OUT std_logic; > clock_10KHz : OUT std_logic; > clock_1KHz : OUT std_logic; > clock_100Hz : OUT std_logic; > clock_10Hz : OUT std_logic; > clock_1Hz : OUT std_logic); > END COMPONENT; > > SIGNAL count : std_logic_vector(3 DOWNTO 0); > SIGNAL clk_1KHz : std_logic; > BEGIN > c0: clk_div port map (clock_25MHz=> clk_25MHz, clock_1KHz=>clk_1KHz); > c1: counter port map (clock=>clk_1KHz, reset=>PB1, count=> count); > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, > led6); > > END c; >
Reply by ●March 7, 20062006-03-07
<sandypure@yahoo.com> wrote in message news:1141751267.321930.165700@v46g2000cwv.googlegroups.com...>I have implemented a 8-bit synchronous counter by VHDL. The result is > that the LED display show continuously running the count from 0 to > F(in Hex). Now, I need to change the result which the LED display can > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > answer me? Thanks a lot!! >How about gating the clock to something really fast when the count is 10 - 15 inclusive. The A-F will whizz by so fast, no-one will notice. If you get that to work, you deserve extra marks. HTH, Syms.
Reply by ●March 7, 20062006-03-07
Alan, I want to ask how to decode in vhdl? When the count is at 9, press reset button is go back to 0 again. Alan Myler =E5=AF=AB=E9=81=93=EF=BC=9A> sandypure@yahoo.com wrote: > > > I have implemented a 8-bit synchronous counter by VHDL. The result is > > that the LED display show continuously running the count from 0 to > > F(in Hex). Now, I need to change the result which the LED display can > > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > > answer me? Thanks a lot!! > > The following VHDL code are about 8-bit synchronous counter: > > Library IEEE; > > USE IEEE.std_logic_1164.all; > > USE IEEE.std_logic_arith.all; > > USE IEEE.std_logic_unsigned.all; > > > > ENTITY counter_eg IS > > PORT( > > PB1, clk_25MHz : IN std_logic; > > led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); > > END counter_eg; > > > > ARCHITECTURE c OF counter_eg IS > > > > COMPONENT counter > > PORT( > > Clock, Reset : IN std_logic; > > count : OUT std_logic_vector(3 DOWNTO 0)); > > > > END COMPONENT; > > > > COMPONENT dec_7seg > > PORT( > > hex_digit : IN std_logic_vector(3 DOWNTO 0); > > segment_a, segment_b, segment_c, segment_d, segment_e, > > segment_f, segment_g : OUT std_logic); > > END COMPONENT; > > > > COMPONENT clk_div > > PORT( > > clock_25MHz : IN std_logic; > > clock_1MHz : OUT std_logic; > > clock_100KHz : OUT std_logic; > > clock_10KHz : OUT std_logic; > > clock_1KHz : OUT std_logic; > > clock_100Hz : OUT std_logic; > > clock_10Hz : OUT std_logic; > > clock_1Hz : OUT std_logic); > > END COMPONENT; > > > > SIGNAL count : std_logic_vector(3 DOWNTO 0); > > SIGNAL clk_1KHz : std_logic; > > BEGIN > > c0: clk_div port map (clock_25MHz=3D> clk_25MHz, clock_1KHz=3D>clk_1K=Hz);> > c1: counter port map (clock=3D>clk_1KHz, reset=3D>PB1, count=3D> coun=t);> > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, > > led6); > > > > END c; > > > > > I'm not going to do your homework for you but here's a suggestion, how > about decoding when the count equals 9 and using this to reset your > counter. For your percentage I'm sure you can figure out how to code > that in your vhdl. >=20 > Alan
Reply by ●March 7, 20062006-03-07
Reply by ●March 7, 20062006-03-07
Reply by ●March 7, 20062006-03-07
Sorry Laura, I was being sarcastic. Of course, gating the clock is BAD! Almost as bad as asking people on a newsgroup to do your homework for you! ;-) Cheers, Syms. <laura_pretty05@yahoo.com.hk> wrote in message news:1141754026.219843.19920@z34g2000cwc.googlegroups.com...> Symon, > gating the clcok?? i don't understand!! Can you explain? Thanks!! >
Reply by ●March 7, 20062006-03-07
Symon wrote:> <sandypure@yahoo.com> wrote in message > news:1141751267.321930.165700@v46g2000cwv.googlegroups.com... > >>I have implemented a 8-bit synchronous counter by VHDL. The result is >>that the LED display show continuously running the count from 0 to >>F(in Hex). Now, I need to change the result which the LED display can >>count from 0 to 9 only. How can I change in the VHDL code? Can anyone >>answer me? Thanks a lot!! >> > > How about gating the clock to something really fast when the count is 10 - > 15 inclusive. The A-F will whizz by so fast, no-one will notice. > If you get that to work, you deserve extra marks. > HTH, Syms.That would only appear to count 0..9, a smart marker might say it still shows A..F just that your eye cannot resolve it... I think the answer is to re-write the FONT ROM code, so it only displays 0..9 - This would even pass a cursory test. ;) - and it appears to fully meet the wording of the spec... -jg
Reply by ●March 8, 20062006-03-08
hi, Aurelian Lazarut I still don't understand what you means. How to decode in VHDL? The following are my counter VHDL code: Library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; Entity Counter IS Port ( Clock, Reset :IN std_logic; count : OUT std_logic_vector(3 DOWNTO 0)); END Counter; ARCHITECTURE a OF Counter IS SIGNAL internal_count: std_logic_vector(3 DOWNTO 0); BEGIN count <=3D internal_count; Process (Reset, Clock) BEGIN IF Reset=3D'0' THEN internal_count <=3D "0000"; ELSIF (Clock'EVENT AND clock=3D'1') THEN internal_count <=3D internal_count + 1; END IF; END Process; END a; from Laura Aurelian Lazarut =E5=AF=AB=E9=81=93=EF=BC=9A> sandypure@yahoo.com wrote: > > I have implemented a 8-bit synchronous counter by VHDL. > > I'll give you a hint, the counter is not in this file, only the > intantiation of the counter. > but you can decode count=3D10 and trigger a reset. (in this file) > as Alan just said. > > Aurash > > The result is > > that the LED display show continuously running the count from 0 to > > F(in Hex). Now, I need to change the result which the LED display can > > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > > answer me? Thanks a lot!! > > The following VHDL code are about 8-bit synchronous counter: > > Library IEEE; > > USE IEEE.std_logic_1164.all; > > USE IEEE.std_logic_arith.all; > > USE IEEE.std_logic_unsigned.all; > > > > ENTITY counter_eg IS > > PORT( > > PB1, clk_25MHz : IN std_logic; > > led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); > > END counter_eg; > > > > ARCHITECTURE c OF counter_eg IS > > > > COMPONENT counter > > PORT( > > Clock, Reset : IN std_logic; > > count : OUT std_logic_vector(3 DOWNTO 0)); > > > > END COMPONENT; > > > > COMPONENT dec_7seg > > PORT( > > hex_digit : IN std_logic_vector(3 DOWNTO 0); > > segment_a, segment_b, segment_c, segment_d, segment_e, > > segment_f, segment_g : OUT std_logic); > > END COMPONENT; > > > > COMPONENT clk_div > > PORT( > > clock_25MHz : IN std_logic; > > clock_1MHz : OUT std_logic; > > clock_100KHz : OUT std_logic; > > clock_10KHz : OUT std_logic; > > clock_1KHz : OUT std_logic; > > clock_100Hz : OUT std_logic; > > clock_10Hz : OUT std_logic; > > clock_1Hz : OUT std_logic); > > END COMPONENT; > > > > SIGNAL count : std_logic_vector(3 DOWNTO 0); > > SIGNAL clk_1KHz : std_logic; > > BEGIN > > c0: clk_div port map (clock_25MHz=3D> clk_25MHz, clock_1KHz=3D>clk_1K=Hz);> > c1: counter port map (clock=3D>clk_1KHz, reset=3D>PB1, count=3D> coun=t);> > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, > > led6); > > =09 > > END c; > >