Questions about counter in VHDL

"Jim Granville" <no.spam@designtools.co.nz> wrote in message 
news:440df96b$1@clear.net.nz...
>
>  I think the answer is to re-write the FONT ROM code, so it only displays 
> 0..9 - This would even pass a cursory test. ;)
>  - and it appears to fully meet the wording of the spec...
> -jg
>
Jim,
Of course! That's an excellent solution. Yet another example of why it's 
unnecessary to gate clocks. :-)
cheers mate, Syms. 

Jim,
   I don't understand what you means. what is Font Rom code?
Laura




Symon =E5=AF=AB=E9=81=93=EF=BC=9A

> "Jim Granville" <no.spam@designtools.co.nz> wrote in message
> news:440df96b$1@clear.net.nz...
> >
> >  I think the answer is to re-write the FONT ROM code, so it only displa=
ys
> > 0..9 - This would even pass a cursory test. ;)
> >  - and it appears to fully meet the wording of the spec...
> > -jg
> >
> Jim,
> Of course! That's an excellent solution. Yet another example of why it's
> unnecessary to gate clocks. :-)
> cheers mate, Syms.

laura_pretty05@yahoo.com.hk wrote:

> Jim,
>    I don't understand what you means. what is Font Rom code?
> Laura

  In your first post, you mentioned a LED display - I assumed 7 Segment
as you said 0..F.
  This needs a lookup table, to convert/map the 4 bit binary, to 
required LEDs - that table is what I call the Font-Rom.
  It is missing from the examples you have posted thus far.

  Have a look at the ISE webpack, WATCHxx.zip examples : these are
a 3 digit stopwatch, and they have all you will need.

-jg

just add a signal

signal clk_counter : std_logic;

change the clock of your counter

c1: counter  port map (clock=>clk_counter , reset=>PB1, count=> count);

and make a process to change the clock of you counter

process(count)
begin
if count = 10 or count=11 or count=12 or count=13 or count=14 or count=15 
then
  clk_counter <= clk_25MHz;
else
  clk_counter <= clock_1Hz ;
end if;
end process;

like this it will count 1 digit each second when betwen 0 to 9 and count so 
fast that no one will notice anything betwen 10 to 15

Regards

kcl

<laura_pretty05@yahoo.com.hk> wrote in message 
news:1141816072.606433.278480@j52g2000cwj.googlegroups.com...
hi, Aurelian Lazarut
I still don't understand what you means. How to decode in VHDL?
The following are my counter VHDL code:
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;


Entity Counter IS
Port
    ( Clock, Reset :IN  std_logic;
     count                 : OUT std_logic_vector(3 DOWNTO 0));
END Counter;

ARCHITECTURE a OF Counter IS
SIGNAL internal_count:  std_logic_vector(3 DOWNTO 0);

BEGIN
count <= internal_count;
Process (Reset, Clock)
    BEGIN
IF Reset='0' THEN
internal_count <= "0000";
ELSIF (Clock'EVENT AND clock='1') THEN
internal_count <= internal_count + 1;
END IF;
    END Process;
END a;

from Laura


Aurelian Lazarut ??:

> sandypure@yahoo.com wrote:
> > I have implemented a 8-bit synchronous counter by VHDL.
>
> I'll give you a hint, the counter is not in this file, only the
> intantiation of the counter.
> but you can decode count=10 and trigger a reset. (in this file)
> as Alan just said.
>
> Aurash
>
>   The result is
> > that the LED display show  continuously running the count from 0 to
> > F(in Hex). Now, I need to change the result which the LED display can
> > count  from 0 to 9 only. How can I change in the VHDL code? Can anyone
> > answer me? Thanks a lot!!
> > The following VHDL code are about 8-bit synchronous counter:
> > Library IEEE;
> > USE IEEE.std_logic_1164.all;
> > USE IEEE.std_logic_arith.all;
> > USE IEEE.std_logic_unsigned.all;
> >
> > ENTITY counter_eg IS
> > PORT(
> >        PB1, clk_25MHz                           : IN std_logic;
> >           led0, led1, led2, led3, led4, led5, led6  : OUT std_logic);
> > END counter_eg;
> >
> > ARCHITECTURE c OF counter_eg IS
> >
> > COMPONENT counter
> > PORT(
> > Clock, Reset : IN  std_logic;
> > count : OUT std_logic_vector(3 DOWNTO 0));
> >
> > END COMPONENT;
> >
> > COMPONENT dec_7seg
> > PORT(
> > hex_digit    : IN std_logic_vector(3 DOWNTO 0);
> > segment_a, segment_b, segment_c, segment_d, segment_e,
> > segment_f, segment_g   : OUT std_logic);
> > END COMPONENT;
> >
> > COMPONENT clk_div
> > PORT(
> > clock_25MHz : IN std_logic;
> > clock_1MHz : OUT std_logic;
> >    clock_100KHz : OUT std_logic;
> >    clock_10KHz : OUT std_logic;
> > clock_1KHz : OUT std_logic;
> > clock_100Hz : OUT std_logic;
> > clock_10Hz : OUT std_logic;
> > clock_1Hz : OUT std_logic);
> > END COMPONENT;
> >
> > SIGNAL count    : std_logic_vector(3 DOWNTO 0);
> > SIGNAL clk_1KHz : std_logic;
> > BEGIN
> > c0: clk_div  port map (clock_25MHz=> clk_25MHz, clock_1KHz=>clk_1KHz);
> > c1: counter  port map (clock=>clk_1KHz, reset=>PB1, count=> count);
> > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5,
> > led6);
> >
> > END c;
> >