a problem with coolrunner CPLD (XC2C256) GCK0 pin

Hello Dear friends
Thanks for all your careful attentions.
I found the solutions. I have set the slew rate setting to slow instead
of fast. When I did this,The jitter came down to .05 UIpp.

Arash Majd

Arash Majd wrote:
> Hello Dear friends
> The board we have designed uses of XC2C256 in its center which
> distributes and switches between different signals in system. We use of
> a timing chip which derives the the output of the optical interface of
> our board. The output clock of the timing chip (named zl_1944_clk)
> which is very exact is 19.44 MHz which we have connected to the CPLD's
> GCK0 input pin and assigned this net to an output on one of the
> ordinary I/O pins to the  clock net of the driving ASIC of the optical
> interface. At this case he measured output jitter on the optical
> interface is approximately 0.12  UIpp and fluctuates unacceptedly
> between 0.08 and 0.15. But when the same signal (zl_1944_clk) is input
> from another input (I/O) port,  the output jitter decreases down to
> 0.05 UIpp. (maenwhile when we bypass the cpld in this net the output
> jitter is 0.07 and doesn't fluctuate that much.)
> Besides, when I get the fitter report of the xilinx ISE 6.1i, it says
> "global clock nets unused".( Although I have connected the zl_1944_clk
> net to GCK0 pin)
> I checked my project with ISE 7.1i, too and it did not work, too.
> I would be grateful if someone help me about this problem and he
> following questions.
>
>
> 1-Is there any point in using GCK0 pin ?
> 2-Should I use of timing constraints to make ISE to route my clock
> signal as desired.
>
> I am under pressure and i should deliver the product as soon as
> possible.
> 
> 
> thanks

Arash Majd wrote:
> Hello Dear friends
> Thanks for all your careful attentions.
> I found the solutions. I have set the slew rate setting to slow instead
> of fast. When I did this,The jitter came down to .05 UIpp.
> 
> Arash Majd

Good to hear you did not need a new PCB design :)
  The fast/slow is not well explained in most data, as it also means
HiDrive/LoDrive, and thus more ground bounce can come from Fast(HiDrive).
  ie unless the last ns matters on long lines, use Slow...

  Did you try fast only on the ClkOUT pin, and Hysteresis on/off on
the clock IP node ?

-jg

I just set the output slew rate to slow (for all pins) in Xilinx ISE
"implement design properties" (considering the fact that its default
was on fast) and it became O.K. I don't know what you mean by clock IP
node?
Jim Granville wrote:
> Arash Majd wrote:
> > Hello Dear friends
> > Thanks for all your careful attentions.
> > I found the solutions. I have set the slew rate setting to slow instead
> > of fast. When I did this,The jitter came down to .05 UIpp.
> >
> > Arash Majd
>
> Good to hear you did not need a new PCB design :)
>   The fast/slow is not well explained in most data, as it also means
> HiDrive/LoDrive, and thus more ground bounce can come from Fast(HiDrive).
>   ie unless the last ns matters on long lines, use Slow...
>
>   Did you try fast only on the ClkOUT pin, and Hysteresis on/off on
> the clock IP node ?
> 
> -jg