Hello group, I have an issue with porting my high-speed DDR interface to Altera Cyclone II device. As far as datasheet says, Altera Cyclone II device does not have any dedicated circuitry to support DDR signaling in its Input/Output blocks for DQ pins. The only thing present in hardware is the clock delay circuitry on DQS pins. All other DDR logic is implemented using LUT's and triggers from adjacent Logic Array Blocks. So, it seams that we have only DQS pins location fixed, whenever all other DDR pins may float within the selected IO bank. Is that right? If yes, then what is the reason to denote certain pins on the Altera Cyclone II package as dedicated pins for DQ input/outputs? With best regards, Vladimir S. Mirgorodsky
Altera Cyclone II DQ/DQS pins location
Started by ●March 18, 2006
Reply by ●March 18, 20062006-03-18
This is a multi-part message in MIME format. ------=_NextPart_000_0007_01C64A80.E6AEC300 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable The DQS signal is usually associated with a group of data (DQ) pins; so = where ever the DQS singal is you want the associated DQ pins located in = close proximity. Also, some DDR2 I/O standards, like SSTL-18 class II, = are only supported on two sides of the chip. <v_mirgorodsky@yahoo.com> wrote in message = news:1142694593.123202.188480@v46g2000cwv.googlegroups.com...> Hello group, >=20 > I have an issue with porting my high-speed DDR interface to Altera > Cyclone II device. As far as datasheet says, Altera Cyclone II device > does not have any dedicated circuitry to support DDR signaling in its > Input/Output blocks for DQ pins. The only thing present in hardware is > the clock delay circuitry on DQS pins. All other DDR logic is > implemented using LUT's and triggers from adjacent Logic Array > Blocks. So, it seams that we have only DQS pins location fixed, > whenever all other DDR pins may float within the selected IO bank. Is > that right? If yes, then what is the reason to denote certain pins on > the Altera Cyclone II package as dedicated pins for DQ input/outputs? >=20 > With best regards, > Vladimir S. Mirgorodsky >------=_NextPart_000_0007_01C64A80.E6AEC300 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2900.2802" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY> <DIV> <P align=3Dleft><FONT face=3DArial size=3D2>The DQS signal is usually = associated with=20 a group of data (DQ) pins; so where ever the DQS singal is you want the=20 associated DQ pins located in close proximity. Also, some DDR2 I/O = standards, like <FONT face=3DHelvetica size=3D1><FONT face=3DArial = size=3D2>SSTL-18=20 class II, are only supported on two sides of the=20 chip.</FONT></P></FONT></FONT></DIV> <DIV><FONT face=3DArial size=3D2><</FONT><A=20 href=3D"mailto:v_mirgorodsky@yahoo.com"><FONT face=3DArial=20 size=3D2>v_mirgorodsky@yahoo.com</FONT></A><FONT face=3DArial = size=3D2>> wrote in=20 message </FONT><A=20 href=3D"news:1142694593.123202.188480@v46g2000cwv.googlegroups.com"><FONT= =20 face=3DArial=20 size=3D2>news:1142694593.123202.188480@v46g2000cwv.googlegroups.com</FONT=></A><FONT=20face=3DArial size=3D2>...</FONT></DIV><FONT face=3DArial size=3D2>> = Hello=20 group,<BR>> <BR>> I have an issue with porting my high-speed DDR = interface=20 to Altera<BR>> Cyclone II device. As far as datasheet says, Altera = Cyclone II=20 device<BR>> does not have any dedicated circuitry to support DDR = signaling in=20 its<BR>> Input/Output blocks for DQ pins. The only thing present in = hardware=20 is<BR>> the clock delay circuitry on DQS pins. All other DDR logic = is<BR>>=20 implemented using LUT's and triggers from adjacent Logic Array<BR>> = Blocks.=20 So, it seams that we have only DQS pins location fixed,<BR>> whenever = all=20 other DDR pins may float within the selected IO bank. Is<BR>> that = right? If=20 yes, then what is the reason to denote certain pins on<BR>> the = Altera=20 Cyclone II package as dedicated pins for DQ input/outputs?<BR>> = <BR>> With=20 best regards,<BR>> Vladimir S. = Mirgorodsky<BR>></FONT></BODY></HTML> ------=_NextPart_000_0007_01C64A80.E6AEC300--
Reply by ●March 18, 20062006-03-18
Hello Rob, Dedicated DQ pins on Altera Cyclone II package have very strange placement and I am curious about the reason those pins are called DQ. In other words, does DQ pin have any significant difference from the adjacent non-DQ pin in the same bank on Altera EP2C8F256 package? With best regards, Vladimir S. Mirgorodsky Rob wrote:> The DQS signal is usually associated with a group of data (DQ) pins; so where ever the DQS > singal is you want the associated DQ pins located in close proximity. Also, some DDR2 I/O > standards, like SSTL-18 class II, are only supported on two sides of the chip. > > <v_mirgorodsky@yahoo.com> wrote in message news:1142694593.123202.188480@v46g2000cwv.googlegroups.com... > > Hello group, > > > > I have an issue with porting my high-speed DDR interface to Altera > > Cyclone II device. As far as datasheet says, Altera Cyclone II device > > does not have any dedicated circuitry to support DDR signaling in its > > Input/Output blocks for DQ pins. The only thing present in hardware is > > the clock delay circuitry on DQS pins. All other DDR logic is > > implemented using LUT's and triggers from adjacent Logic Array > > Blocks. So, it seams that we have only DQS pins location fixed, > > whenever all other DDR pins may float within the selected IO bank. Is > > that right? If yes, then what is the reason to denote certain pins on > > the Altera Cyclone II package as dedicated pins for DQ input/outputs? > > > > With best regards, > > Vladimir S. Mirgorodsky
Reply by ●March 18, 20062006-03-18
What are you trying to do? If you're not using the DQ pins for a memory interface then treat them as standard I/O. <v_mirgorodsky@yahoo.com> wrote in message news:1142707551.809050.269660@u72g2000cwu.googlegroups.com...> Hello Rob, > > Dedicated DQ pins on Altera Cyclone II package have very strange > placement and I am curious about the reason those pins are called DQ. > In other words, does DQ pin have any significant difference from the > adjacent non-DQ pin in the same bank on Altera EP2C8F256 package? > > With best regards, > Vladimir S. Mirgorodsky > > > Rob wrote: >> The DQS signal is usually associated with a group of data (DQ) pins; so >> where ever the DQS >> singal is you want the associated DQ pins located in close proximity. >> Also, some DDR2 I/O >> standards, like SSTL-18 class II, are only supported on two sides of the >> chip. >> >> <v_mirgorodsky@yahoo.com> wrote in message >> news:1142694593.123202.188480@v46g2000cwv.googlegroups.com... >> > Hello group, >> > >> > I have an issue with porting my high-speed DDR interface to Altera >> > Cyclone II device. As far as datasheet says, Altera Cyclone II device >> > does not have any dedicated circuitry to support DDR signaling in its >> > Input/Output blocks for DQ pins. The only thing present in hardware is >> > the clock delay circuitry on DQS pins. All other DDR logic is >> > implemented using LUT's and triggers from adjacent Logic Array >> > Blocks. So, it seams that we have only DQS pins location fixed, >> > whenever all other DDR pins may float within the selected IO bank. Is >> > that right? If yes, then what is the reason to denote certain pins on >> > the Altera Cyclone II package as dedicated pins for DQ input/outputs? >> > >> > With best regards, >> > Vladimir S. Mirgorodsky >
Reply by ●March 19, 20062006-03-19
Hello Vladimir, DQS/DQ/DM-placement is important. The DDR interface requires correct placement of the LEs and routing to the IOB. Quartus does this only for the DQ-pins specified in the datasheet (even it would maybe be possible for other pins as well by the hardware, but the software does not support this). In my design I had mixed up some DM and DQ-pins (I believed that are handled equally when I made the layout, but this is not the case) -> 3 of my 32 DQ pins are not recognized as DQ pins and the design does not compile. (I found a workaround for the prototypes, but require a layout-change for mass-production...) Regards, Thomas www.entner-electronics.com <v_mirgorodsky@yahoo.com> schrieb im Newsbeitrag news:1142694593.123202.188480@v46g2000cwv.googlegroups.com...> Hello group, > > I have an issue with porting my high-speed DDR interface to Altera > Cyclone II device. As far as datasheet says, Altera Cyclone II device > does not have any dedicated circuitry to support DDR signaling in its > Input/Output blocks for DQ pins. The only thing present in hardware is > the clock delay circuitry on DQS pins. All other DDR logic is > implemented using LUT's and triggers from adjacent Logic Array > Blocks. So, it seams that we have only DQS pins location fixed, > whenever all other DDR pins may float within the selected IO bank. Is > that right? If yes, then what is the reason to denote certain pins on > the Altera Cyclone II package as dedicated pins for DQ input/outputs? > > With best regards, > Vladimir S. Mirgorodsky >
