How to write a correct code to do 2 writes to an array on same cycle?

On Thursday, September 26, 2019 at 9:36:46 AM UTC-4, Weng Tianxiang wrote:
> On Thursday, September 26, 2019 at 2:50:48 AM UTC-7, HT-Lab wrote:
> > On 25/09/2019 22:22, Weng Tianxiang wrote:
> > > On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote:
> > >> On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wrote:
> > ..
> > > p1: process(CLK) is
> > > begin
> > >    if CLK'event and CLK = '1' then
> > >      if C1 then
> > >        An_Array(a) <= D1;
> > >      end if;
> > > 
> > >      -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.
> > >   
> > >      if_2 C2 then
> > >        An_Array(b) <= D2;
> > >      end if;
> > >    end if;
> > > end process;
> > > 
> > > Using the new suggested keyword "if_2" in VHDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chip.
> > > 
> > > In my design there are more than 10 arrays need 2-write port memory.
> > > 
> > > Weng
> > > 
> > 
> > Hi Weng,
> > 
> > Give it up, your are flogging a dead horse, no new language constructs 
> > are requires as we already have the correct simulation and synthesis 
> > models for decades.
> > 
> > If you have lots of dual port memories to connect use a Generate statement.
> > 
> > Regards,
> > Hans
> > www.ht-lab.com
> 
> Hans,
> 
> Here is an excellent paper dealing with the situation: efficient multi-port memory with FPGA, http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf.
> 
> I appreciate the paper very much. I know there is a solution to 2-write memory, but simple "if_2" is a simple solution to inferring to the method.
> 
> Weng

You have provided a keyword, "if_2" and a code example which is not logically correct.  I don't see how your keyword solves anything.  First, you need to define exactly what the keyword does, which I assume is the same as "if".  Then you need to use examples which are logically correct.  Then perhaps you can explain why your new keyword accomplishes something that the existing keyword doesn't do already. 

It sure seems like you are trying to solve a problem that doesn't exist.  Certainly your initial premise that dual write port RAMs must be instantiated is not correct.  Dual write port RAMs can be inferred as shown in the info I linked to in the other thread. 

-- 

  Rick C.

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On 26/09/2019 14:36, Weng Tianxiang wrote:
> On Thursday, September 26, 2019 at 2:50:48 AM UTC-7, HT-Lab wrote:
>> On 25/09/2019 22:22, Weng Tianxiang wrote:
..
>>
>> Hi Weng,
>>
>> Give it up, your are flogging a dead horse, no new language constructs
>> are requires as we already have the correct simulation and synthesis
>> models for decades.
>>
>> If you have lots of dual port memories to connect use a Generate statement.
>>
>> Regards,
>> Hans
>> www.ht-lab.com
> 
> Hans,
> 
> Here is an excellent paper dealing with the situation: efficient multi-port memory with FPGA, http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf.
> 
> I appreciate the paper very much. I know there is a solution to 2-write memory, but simple "if_2" is a simple solution to inferring to the method.
> 
> Weng

Hi Weng,

Yes I know that paper quite well and have used the XOR variant in one of 
my x86 processors (4W8R). I had no problems implementing it, the 
standard method is simple and straightforward.

As others have told you multi port memories are well established and 
understood in our community, there is no need for a special keyword.

Regards,
Hans
www.ht-lab.com

On Thursday, September 26, 2019 at 9:36:46 AM UTC-4, Weng Tianxiang wrote:

> 
> Here is an excellent paper dealing with the situation: efficient multi-port memory with FPGA, http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf.
> 
> I appreciate the paper very much. I know there is a solution to 2-write memory, but simple "if_2" is a simple solution to inferring to the method.
> 

If_2 is not the solution to inferring the method by LaForest and Steffan.  In a nutshell, what they describe is the bolded text in section 5 (LVT-Based Multiported memories) where it clearly says "Our approach comprises
banks of replicated block RAMs where a mechanism of indirection...".  They are not claiming to implement something that implements the two write port hardware description that you presented.  There would still need to be code written to implement the LVT approach in order to describe that LVT design.  Once that code is written, one would have a multi-port design that one could reuse but it would use more logic/memory resources than just a memory.

If you think the LVT based approach is worth using for your design, then write the code to implement an LVT based memory design.  Trying to propose 'if_2' as being some way to implement LVT (or some other alternative approach) is quite naive on your part.

Kevin Jennings