Forums

Programming a Traffic Light Controller In verilog using Quartus Prime Lite

Started by Dave Wood November 18, 2020
Hi everyone,
 ( Don't know if this is even the right place to post a question but ill tr=
y my luck)
So basically I am a student and I have a final project to build a traffic l=
ight control system using Verilog, and then I am to program my FPGA board w=
hich is a De10-lite. I feel like the coding aspect of the project isn't bad=
. I have cases and such set up to switch the device to different states bas=
ed on clock pulses and user input on the FPGA board. My one question is: ho=
w am I supposed to translate my code that I've been working hard on and mak=
e it so it will work with the FPGA board. I need my lights to work as the t=
raffic lights ( both north-south and east- west roads) and I have pedestria=
n walk signals that can interrupt the traffic lights to let pedestrians cro=
ss as well as off peak and peak times determined by a switch. I don't reall=
y know how to translate the code into a function device and the resources I=
've been trying to find have been less than helpful. If this isn't the corr=
ect spot to post something about this particular issue could someone point =
me in a direction that can be helpful? Or if this is a spot to get some hel=
p? I would greatly appreciate all the help I can get.
Thanks in advance,
Dave Wood=20
T24gMTEvMTgvMjAgMTA6NDkgUE0sIERhdmUgV29vZCB3cm90ZToNCj4gSGkgZXZlcnlvbmUs
DQo+ICAoIERvbid0IGtub3cgaWYgdGhpcyBpcyBldmVuIHRoZSByaWdodCBwbGFjZSB0byBw
b3N0IGEgcXVlc3Rpb24gYnV0IGlsbCB0cnkgbXkgbHVjaykNCj4gU28gYmFzaWNhbGx5IEkg
YW0gYSBzdHVkZW50IGFuZCBJIGhhdmUgYSBmaW5hbCBwcm9qZWN0IHRvIGJ1aWxkIGEgdHJh
ZmZpYyBsaWdodCBjb250cm9sIHN5c3RlbSB1c2luZyBWZXJpbG9nLCBhbmQgdGhlbiBJIGFt
IHRvIHByb2dyYW0gbXkgRlBHQSBib2FyZCB3aGljaCBpcyBhIERlMTAtbGl0ZS4gSSBmZWVs
IGxpa2UgdGhlIGNvZGluZyBhc3BlY3Qgb2YgdGhlIHByb2plY3QgaXNuJ3QgYmFkLiBJIGhh
dmUgY2FzZXMgYW5kIHN1Y2ggc2V0IHVwIHRvIHN3aXRjaCB0aGUgZGV2aWNlIHRvIGRpZmZl
cmVudCBzdGF0ZXMgYmFzZWQgb24gY2xvY2sgcHVsc2VzIGFuZCB1c2VyIGlucHV0IG9uIHRo
ZSBGUEdBIGJvYXJkLiBNeSBvbmUgcXVlc3Rpb24gaXM6IGhvdyBhbSBJIHN1cHBvc2VkIHRv
IHRyYW5zbGF0ZSBteSBjb2RlIHRoYXQgSSd2ZSBiZWVuIHdvcmtpbmcgaGFyZCBvbiBhbmQg
bWFrZSBpdCBzbyBpdCB3aWxsIHdvcmsgd2l0aCB0aGUgRlBHQSBib2FyZC4gSSBuZWVkIG15
IGxpZ2h0cyB0byB3b3JrIGFzIHRoZSB0cmFmZmljIGxpZ2h0cyAoIGJvdGggbm9ydGgtc291
dGggYW5kIGVhc3QtIHdlc3Qgcm9hZHMpIGFuZCBJIGhhdmUgcGVkZXN0cmlhbiB3YWxrIHNp
Z25hbHMgdGhhdCBjYW4gaW50ZXJydXB0IHRoZSB0cmFmZmljIGxpZ2h0cyB0byBsZXQgcGVk
ZXN0cmlhbnMgY3Jvc3MgYXMgd2VsbCBhcyBvZmYgcGVhayBhbmQgcGVhayB0aW1lcyBkZXRl
cm1pbmVkIGJ5IGEgc3dpdGNoLiBJIGRvbid0IHJlYWxseSBrbm93IGhvdyB0byB0cmFuc2xh
dGUgdGhlIGNvZGUgaW50byBhIGZ1bmN0aW9uIGRldmljZSBhbmQgdGhlIHJlc291cmNlcyBJ
J3ZlIGJlZW4gdHJ5aW5nIHRvIGZpbmQgaGF2ZSBiZWVuIGxlc3MgdGhhbiBoZWxwZnVsLiBJ
ZiB0aGlzIGlzbid0IHRoZSBjb3JyZWN0IHNwb3QgdG8gcG9zdCBzb21ldGhpbmcgYWJvdXQg
dGhpcyBwYXJ0aWN1bGFyIGlzc3VlIGNvdWxkIHNvbWVvbmUgcG9pbnQgbWUgaW4gYSBkaXJl
Y3Rpb24gdGhhdCBjYW4gYmUgaGVscGZ1bD8gT3IgaWYgdGhpcyBpcyBhIHNwb3QgdG8gZ2V0
IHNvbWUgaGVscD8gSSB3b3VsZCBncmVhdGx5IGFwcHJlY2lhdGUgYWxsIHRoZSBoZWxwIEkg
Y2FuIGdldC4NCj4gVGhhbmtzIGluIGFkdmFuY2UsDQo+IERhdmUgV29vZCANCj4gDQoNCk1v
c3QgRlBHQXMgaGF2ZSBlbm91Z2ggZHJpdmUgc3RyZW5ndGggdGhhdCB5b3UgY2FuIGp1c3Qg
Y29ubmVjdCBhbiBMRUQNCih3aXRoIGN1cnJlbnQgbGltaXRpbmcgcmVzaXN0b3IpIHRvIHRo
ZSBvdXRwdXQgYW5kIGl0IGNhbiBtYWtlIGl0IGdsb3cNCm9yIG5vdC4gU2ltaWxhcmx5LCBh
IHN3aXRjaCAod2l0aCBhIHB1bGwgdXAgcmVzaXN0b3IpIGNhbiBiZSBicm91Z2h0DQppbnRv
IGFuIGlucHV0IHBpbiBhIGRldmljZS4NCg0KWW91ciBkZXNpZ24gd2lsbCBoYXZlIGEgbW9k
dWxlIGF0IGl0cyB0b3AgbGV2ZWwsIGFuZCB0aGUgaW5wdXRzIGFuZA0Kb3V0cHV0cyBvZiB0
aGUgbWFkdWxlIHdpbGwgYmVjb21lIHBpbnMgb2YgdGhlIGRldmljZS4gWW91IHdpbGwgbmVl
ZCB0bw0KdXNlIGZlYXR1cmVzIG9mIHRoZSBGUEdBIGRlc2lnbiBzb2Z0d2FyZSB0byBtYXAg
eW91ciBtb2R1bGUgaW5wdXRzIGFuZA0Kb3V0cHV0cyB0byB0aGUgc3BlY2lmaWMgcGlucyB5
b3UgaGF2ZSBhdHRhY2hlZCB0aGUgc3dpdGNoZXMgYW5kIExFRHMgdG8uDQoNCg0KSXQgbG9v
a3MgbGlrZSB0aGF0IGJvYXJkIGFscmVhZHkgaGFzIGEgbnVtYmVyIG9mIGRpc3BsYXlzIGFu
ZCBzd2l0Y2hlcw0KYXR0YWNoZWQsIHNvIGZpcnN0IHlvdSBuZWVkIHRvIGRlY2lkZSBob3cg
dG8gbWFwIHRoZSBwYXJ0cyBvZiB0aGUgYm9hcmQNCnRvIHlvdXIgJ3RyYWZmaWMgbGlndHMn
IGFuZCBpbnB1dHMuIFRoZW4geW91IG5lZWQgdG8gZmluZCBvdXQgd2hhdCBwaW5zDQp0aG9z
ZSBjb25uZWN0IHRvIHdpdGggdGhlIGRvY3VtZW50YXRpb24gb2YgdGhlIGJvYXJkLiBUaGVu
IHlvdSBjYW4gdXNlDQp0aGUgRlBHQSBzb2Z0d2FyZSB0byBtYXAgdGhvc2UgcGlucyB0byB5
b3VyIHNpZ25hbHMuDQo=
Richard Damon <Richard@damon-family.org> wrote:
> It looks like that board already has a number of displays and switches > attached, so first you need to decide how to map the parts of the board > to your 'traffic ligts' and inputs. Then you need to find out what pins > those connect to with the documentation of the board. Then you can use > the FPGA software to map those pins to your signals.
Unless the OP already has a template design (eg from their professor) it might be worth starting with an example project that already targets that board. If you download the 'DE10Lite CD-ROM' (which is a Zipfile, don't know why they call it a CD) from here: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021&PartNo=4 (requires login) there's usually a series of example projects. Terasic usually provide a 'Golden Top' project which is an empty shell that's ready for you to drop your code into (there are other projects for talking to things like Ethernet and off-chip memory, which you don't need for now). Wiring up your code to the clock and LEDs provided in that project should be fairly straightforward (a few minutes work), and then you can build it in Quartus. Theo
Theo <theom+news@chiark.greenend.org.uk> wrote:
> Wiring up your code to the clock and LEDs provided in that project should be > fairly straightforward (a few minutes work), and then you can build it in > Quartus.
PS My brief guide to using Quartus: https://www.cl.cam.ac.uk/teaching/2021/ECAD+Arch/exercise-fpga.html