DDR Termination

I am creating a design using a Xilinx Virtex II Pro and some DDR memory. I
downloaded the Xilinx ML361 DDR Ref design to get some tips. They have put
resistors on the appropriate tracks to VTT at both the DDR and FPGA. I was
going to put the resistor at the DDR but use the FPGAs DCI to terminate at
the FPGA using a series resistance. Can I do this or have I missed a trick
somewhere along.

Cheers

Jon

"maxascent" <maxascent@yahoo.co.uk> wrote in message 
news:j5ednbW2A7vePqrZRVn_vA@giganews.com...
>
> I am creating a design using a Xilinx Virtex II Pro and some DDR memory. I
> downloaded the Xilinx ML361 DDR Ref design to get some tips. They have put
> resistors on the appropriate tracks to VTT at both the DDR and FPGA. I was
> going to put the resistor at the DDR but use the FPGAs DCI to terminate at
> the FPGA using a series resistance. Can I do this or have I missed a trick
> somewhere along.
>
> Cheers
>
> Jon

Jon,

You have to carefully look at what the DCI options are for a particular type 
of line. The V2-Pro user guide is the best source of this information. As I 
recall, the 25 (22?) ohm series output is only available by itself when the 
IOB is an output (only). If the IOB is bidir (as is the case for the DQ and 
DQS lines) then you also get the two parallel (supply-to-ground) 100 ohm 
terminations. These get the FPGA really hot if you're using a lot of IOBs, 
in this configuration. Also, I believe that there are different DCI options 
depending on whether you're using Class I or Class II SSTL.

The best thing to do is to simulate the entire ram circuit and see what type 
of termination you really need. As long as you meet your setup and hold 
times, and don't violate the undershoot/overshoot specs of the ram and FPGA, 
you may be able to simplify the termination scheme.

Bob