Did National cheat with the Virtex 4

> Providing mindless rules without a good reason can just lead to more headaches.
I would have to leave this one to the Altera guys.  I am not sure if
they would view it as a mindless rule or not.

I have a call into National.  I will post their responce.

Austin Lesea wrote:
> engineers for decades have used components "outside" of their stated
> specifications.
> 
> The 'penalty' for being caught, is that the manufacturer may state
> that the usage is not covered by the specifications, and thus, not
> guaranteed.

lecroy7200 wrote:
> That was my question.  Is this the level of support we would expect
> from Xilinx?

Depends on who "we" are.  If you buy $10K of Xilinx parts per year, I
expect they're not going to go as far out of their way to support you as
if you buy $10M per year.  Like any other business, Xilinx has finite
resources available to support customers, and has to devote them in such
a way as to maximize return.  That's part of their fiduciary
responsibility to their shareholders.

If a small customer wants to deliberately use a part outside its specs,
the answer is probably "you're on your own", but if i vary big customer
wants it, they can probably get Xilinx to have engineering resources
assigned to validating and/or qualifying the part at the desired specs.

That said, in my experience Xilinx does a very good job of supporting
small customers, within the limits of what can reasonably be expected.

Eric

lecroy7200@chek.com wrote:
>
> At 9:04 Ian states ".. you will create a 750MHz, ah.." Interrupted by
> H.J.
>
> If they ran it using DDR mode, I would think they would not have made a
> point to call out the 750MHz clock.
>

 Thanks for the detailed timeline; although the clock on the nearby
slide is labeled '750 MHz LVDS', shortly after that "ah..",  H.J.
refers to the 750 MHz as an "output rate".

 Also, there's a link on the video page to the Xcell article:
http://www.xilinx.com/publications/xcellonline/xcell_56/xc_pdf/xc_gigasample56.pdf

which says:
 "For a 1.5 GHz sample rate, the conversion data will be output
synchronous to a 750 MHz clock. Even at this reduced speed,
FPGA memories and latches would not be able to accept this data
directly. It is therefore beneficial to make use of a DDR method, where
data is presented to the outputs on the both the rising and falling
edges of the clock (Figure 4).

Although the data rate remains the same for DDR signaling, the
clock frequency is halved again to a more manageable 375 MHz"


Brian

>
>  Thanks for the detailed timeline; although the clock on the nearby
> slide is labeled '750 MHz LVDS', shortly after that "ah..",  H.J.
> refers to the 750 MHz as an "output rate".
>
>  Also, there's a link on the video page to the Xcell article:
> http://www.xilinx.com/publications/xcellonline/xcell_56/xc_pdf/xc_gigasample56.pdf
>
> which says:
>  "For a 1.5 GHz sample rate, the conversion data will be output
> synchronous to a 750 MHz clock. Even at this reduced speed,
> FPGA memories and latches would not be able to accept this data
> directly. It is therefore beneficial to make use of a DDR method, where
> data is presented to the outputs on the both the rising and falling
> edges of the clock (Figure 4).

Talking with National, they stated that when running the Virtex 4 at
750MHz that they saw about a 20 deg. C rise.  Other than this they saw
no problems.  They saw no reason to run the part in this mode and
switched.  It sounds like the board still supports both modes.  I guess
the video was right, but they had a change in heart.