On Sat, 14 Jan 2023 21:04:55 -0800 (PST), "gnuarm.del...@gmail.com" <gnuarm.deletethisbit@gmail.com> wrote:>On Sunday, January 15, 2023 at 12:10:54 AM UTC-4, John Larkin wrote: >> On Sat, 14 Jan 2023 17:52:45 -0800 (PST), "gnuarm.del...@gmail.com" >> <gnuarm.del...@gmail.com> wrote: >> >> >On Saturday, January 14, 2023 at 9:34:09 PM UTC-4, John Larkin wrote: >> >> On Sat, 14 Jan 2023 16:20:53 -0800 (PST), "gnuarm.del...@gmail.com" >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >On Saturday, January 14, 2023 at 3:17:24 PM UTC-4, John Larkin wrote: >> >> >> On Sat, 14 Jan 2023 10:05:33 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >On Saturday, January 14, 2023 at 12:08:03 PM UTC-4, John Larkin wrote: >> >> >> >> On Fri, 13 Jan 2023 21:20:50 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >On Saturday, January 14, 2023 at 12:39:49 AM UTC-4, John Larkin wrote: >> >> >> >> >> On Sat, 7 Jan 2023 09:49:24 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >> >> >A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! >> >> >> >> >> > >> >> >> >> >> >So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find that fit on the board have 196 or 256 pins. But the real problem is availability. >> >> >> >> >> > >> >> >> >> >> >Digikey has a few of the XC7S15-1FTGB196I and more a scheduled for delivery in April. Add in the various speed and temperature flavors trickling in (mostly in April) and I should be ok for the initial delivery in August... if I can get my hands on those. I don't know if Digikey factors in the backlog orders in these counts. >> >> >> >> >> > >> >> >> >> >> >Mouser shows great inventory of Efinix parts, particularly the T13 and T20 in a 0.8 mm 256 pin BGA, 10s of thousands in stock. But I'd rather work with a 1.0 mm BGA. Oddly enough, LCSC shows part numbers, but zero inventory. >> >> >> >> >> > >> >> >> >> >> >Anyone work with 0.8 mm BGAs? What PWB feature dimensions did you use? Did this impact the PWB cost? >> >> >> >> >> The 0.8 mm 256-ball T20 isn't bad... >> >> >> >> >> >> >> >> >> >> https://www.dropbox.com/s/xjqgj2pz9mdhtma/P941_FPGA.jpg?raw=1 >> >> >> >> > >> >> >> >> >I can't really see much detail. It looks like there are virtually no pads on the vias under the BGA. What size are they? >> >> >> >> The BGAVIAs are 12.5 mil OD with 8 mil drills. The other vias on the >> >> >> >> board STANDARDVIA and POWERVIA are bigger. >> >> >> > >> >> >> >2.25 mil (0.057 mm) is a pretty narrow via ring. Why not have a larger via pad? >> >> >> I don't know. My PCB guy decides stuff like that. I'd guess that he >> >> >> wanted it to pass some design rule check, or maybe he started metric. >> >> >> The board houses haven't complained as far as I know. >> >> >> >> >> >> You should do your own thing and check with whoever will make your >> >> >> boards. >> >> > >> >> >Sounds good, but I've never been able to get a board house to even discuss these issues. They always take the approach that they will work with what I give them, which means, if it gives poor results, it's my problem. >> >> We always specify bare-board testing and warpage and tolerances, so we >> >> don't get bad boards. What we can get is expensive boards. >> >> > >> >> >There are a number of board companies with published capabilities, but they all vary, enough that there seems to be no consensus. Just like your via pad size. I've never seen a board house that says that would be a standard board. I was just looking at one company who wants 10 mil annular ring on inner layers and 7 mil annular ring on surface layers. That's a huge difference from 2.25 mil. On the other hand, they will print 2.5 mil trace/space! >> >> Zero annular ring seems to be OK on inners. That reduces capacitance. >> >> 5 or even 4 mil traces are usually standard price. I don't know why my >> >> guy used 6 on the board that I posted. >> >> >> >> We do email our board houses and often they answer! >> > >> >You aren't paying attention. >> That's because you're obnoxious. > >Wow! Talk about sensitive. What is going on with you???Just trying to help. My mistake.
PCB Layout for BGAs
Started by ●January 7, 2023
Reply by ●January 15, 20232023-01-15
Reply by ●January 16, 20232023-01-16
On Sunday, January 15, 2023 at 2:37:04 PM UTC-4, John Larkin wrote:> On Sat, 14 Jan 2023 21:04:55 -0800 (PST), "gnuarm.del...@gmail.com" > <gnuarm.del...@gmail.com> wrote: > > >On Sunday, January 15, 2023 at 12:10:54 AM UTC-4, John Larkin wrote: > >> On Sat, 14 Jan 2023 17:52:45 -0800 (PST), "gnuarm.del...@gmail.com" > >> <gnuarm.del...@gmail.com> wrote: > >> > >> >On Saturday, January 14, 2023 at 9:34:09 PM UTC-4, John Larkin wrote: > >> >> On Sat, 14 Jan 2023 16:20:53 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> <gnuarm.del...@gmail.com> wrote: > >> >> > >> >> >On Saturday, January 14, 2023 at 3:17:24 PM UTC-4, John Larkin wrote: > >> >> >> On Sat, 14 Jan 2023 10:05:33 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> >> <gnuarm.del...@gmail.com> wrote: > >> >> >> > >> >> >> >On Saturday, January 14, 2023 at 12:08:03 PM UTC-4, John Larkin wrote: > >> >> >> >> On Fri, 13 Jan 2023 21:20:50 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> >> >> <gnuarm.del...@gmail.com> wrote: > >> >> >> >> > >> >> >> >> >On Saturday, January 14, 2023 at 12:39:49 AM UTC-4, John Larkin wrote: > >> >> >> >> >> On Sat, 7 Jan 2023 09:49:24 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: > >> >> >> >> >> > >> >> >> >> >> >A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! > >> >> >> >> >> > > >> >> >> >> >> >So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find that fit on the board have 196 or 256 pins. But the real problem is availability. > >> >> >> >> >> > > >> >> >> >> >> >Digikey has a few of the XC7S15-1FTGB196I and more a scheduled for delivery in April. Add in the various speed and temperature flavors trickling in (mostly in April) and I should be ok for the initial delivery in August... if I can get my hands on those. I don't know if Digikey factors in the backlog orders in these counts. > >> >> >> >> >> > > >> >> >> >> >> >Mouser shows great inventory of Efinix parts, particularly the T13 and T20 in a 0.8 mm 256 pin BGA, 10s of thousands in stock. But I'd rather work with a 1.0 mm BGA. Oddly enough, LCSC shows part numbers, but zero inventory. > >> >> >> >> >> > > >> >> >> >> >> >Anyone work with 0.8 mm BGAs? What PWB feature dimensions did you use? Did this impact the PWB cost? > >> >> >> >> >> The 0.8 mm 256-ball T20 isn't bad... > >> >> >> >> >> > >> >> >> >> >> https://www.dropbox.com/s/xjqgj2pz9mdhtma/P941_FPGA.jpg?raw=1 > >> >> >> >> > > >> >> >> >> >I can't really see much detail. It looks like there are virtually no pads on the vias under the BGA. What size are they? > >> >> >> >> The BGAVIAs are 12.5 mil OD with 8 mil drills. The other vias on the > >> >> >> >> board STANDARDVIA and POWERVIA are bigger. > >> >> >> > > >> >> >> >2.25 mil (0.057 mm) is a pretty narrow via ring. Why not have a larger via pad? > >> >> >> I don't know. My PCB guy decides stuff like that. I'd guess that he > >> >> >> wanted it to pass some design rule check, or maybe he started metric. > >> >> >> The board houses haven't complained as far as I know. > >> >> >> > >> >> >> You should do your own thing and check with whoever will make your > >> >> >> boards. > >> >> > > >> >> >Sounds good, but I've never been able to get a board house to even discuss these issues. They always take the approach that they will work with what I give them, which means, if it gives poor results, it's my problem. > >> >> We always specify bare-board testing and warpage and tolerances, so we > >> >> don't get bad boards. What we can get is expensive boards. > >> >> > > >> >> >There are a number of board companies with published capabilities, but they all vary, enough that there seems to be no consensus. Just like your via pad size. I've never seen a board house that says that would be a standard board. I was just looking at one company who wants 10 mil annular ring on inner layers and 7 mil annular ring on surface layers. That's a huge difference from 2.25 mil. On the other hand, they will print 2.5 mil trace/space! > >> >> Zero annular ring seems to be OK on inners. That reduces capacitance. > >> >> 5 or even 4 mil traces are usually standard price. I don't know why my > >> >> guy used 6 on the board that I posted. > >> >> > >> >> We do email our board houses and often they answer! > >> > > >> >You aren't paying attention. > >> That's because you're obnoxious. > > > >Wow! Talk about sensitive. What is going on with you??? > Just trying to help. My mistake.Dude, you are way too sensitive. Chillax! You'll live longer. -- Rick C. -+-- Get 1,000 miles of free Supercharging -+-- Tesla referral code - https://ts.la/richard11209
Reply by ●January 16, 20232023-01-16
On Sun, 15 Jan 2023 20:11:34 -0800 (PST), "gnuarm.del...@gmail.com" <gnuarm.deletethisbit@gmail.com> wrote:>On Sunday, January 15, 2023 at 2:37:04 PM UTC-4, John Larkin wrote: >> On Sat, 14 Jan 2023 21:04:55 -0800 (PST), "gnuarm.del...@gmail.com" >> <gnuarm.del...@gmail.com> wrote: >> >> >On Sunday, January 15, 2023 at 12:10:54 AM UTC-4, John Larkin wrote: >> >> On Sat, 14 Jan 2023 17:52:45 -0800 (PST), "gnuarm.del...@gmail.com" >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >On Saturday, January 14, 2023 at 9:34:09 PM UTC-4, John Larkin wrote: >> >> >> On Sat, 14 Jan 2023 16:20:53 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >On Saturday, January 14, 2023 at 3:17:24 PM UTC-4, John Larkin wrote: >> >> >> >> On Sat, 14 Jan 2023 10:05:33 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >On Saturday, January 14, 2023 at 12:08:03 PM UTC-4, John Larkin wrote: >> >> >> >> >> On Fri, 13 Jan 2023 21:20:50 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >> >> >On Saturday, January 14, 2023 at 12:39:49 AM UTC-4, John Larkin wrote: >> >> >> >> >> >> On Sat, 7 Jan 2023 09:49:24 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >> >> >> >> >A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! >> >> >> >> >> >> > >> >> >> >> >> >> >So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find that fit on the board have 196 or 256 pins. But the real problem is availability. >> >> >> >> >> >> > >> >> >> >> >> >> >Digikey has a few of the XC7S15-1FTGB196I and more a scheduled for delivery in April. Add in the various speed and temperature flavors trickling in (mostly in April) and I should be ok for the initial delivery in August... if I can get my hands on those. I don't know if Digikey factors in the backlog orders in these counts. >> >> >> >> >> >> > >> >> >> >> >> >> >Mouser shows great inventory of Efinix parts, particularly the T13 and T20 in a 0.8 mm 256 pin BGA, 10s of thousands in stock. But I'd rather work with a 1.0 mm BGA. Oddly enough, LCSC shows part numbers, but zero inventory. >> >> >> >> >> >> > >> >> >> >> >> >> >Anyone work with 0.8 mm BGAs? What PWB feature dimensions did you use? Did this impact the PWB cost? >> >> >> >> >> >> The 0.8 mm 256-ball T20 isn't bad... >> >> >> >> >> >> >> >> >> >> >> >> https://www.dropbox.com/s/xjqgj2pz9mdhtma/P941_FPGA.jpg?raw=1 >> >> >> >> >> > >> >> >> >> >> >I can't really see much detail. It looks like there are virtually no pads on the vias under the BGA. What size are they? >> >> >> >> >> The BGAVIAs are 12.5 mil OD with 8 mil drills. The other vias on the >> >> >> >> >> board STANDARDVIA and POWERVIA are bigger. >> >> >> >> > >> >> >> >> >2.25 mil (0.057 mm) is a pretty narrow via ring. Why not have a larger via pad? >> >> >> >> I don't know. My PCB guy decides stuff like that. I'd guess that he >> >> >> >> wanted it to pass some design rule check, or maybe he started metric. >> >> >> >> The board houses haven't complained as far as I know. >> >> >> >> >> >> >> >> You should do your own thing and check with whoever will make your >> >> >> >> boards. >> >> >> > >> >> >> >Sounds good, but I've never been able to get a board house to even discuss these issues. They always take the approach that they will work with what I give them, which means, if it gives poor results, it's my problem. >> >> >> We always specify bare-board testing and warpage and tolerances, so we >> >> >> don't get bad boards. What we can get is expensive boards. >> >> >> > >> >> >> >There are a number of board companies with published capabilities, but they all vary, enough that there seems to be no consensus. Just like your via pad size. I've never seen a board house that says that would be a standard board. I was just looking at one company who wants 10 mil annular ring on inner layers and 7 mil annular ring on surface layers. That's a huge difference from 2.25 mil. On the other hand, they will print 2.5 mil trace/space! >> >> >> Zero annular ring seems to be OK on inners. That reduces capacitance. >> >> >> 5 or even 4 mil traces are usually standard price. I don't know why my >> >> >> guy used 6 on the board that I posted. >> >> >> >> >> >> We do email our board houses and often they answer! >> >> > >> >> >You aren't paying attention. >> >> That's because you're obnoxious. >> > >> >Wow! Talk about sensitive. What is going on with you??? >> Just trying to help. My mistake. > >Dude, you are way too sensitive. Chillax! You'll live longer.Stop being obnoxious and you'll get more help. But not fom me.
Reply by ●January 16, 20232023-01-16
On Monday, January 16, 2023 at 11:04:28 AM UTC-4, John Larkin wrote:> On Sun, 15 Jan 2023 20:11:34 -0800 (PST), "gnuarm.del...@gmail.com" > <gnuarm.del...@gmail.com> wrote: > > >On Sunday, January 15, 2023 at 2:37:04 PM UTC-4, John Larkin wrote: > >> On Sat, 14 Jan 2023 21:04:55 -0800 (PST), "gnuarm.del...@gmail.com" > >> <gnuarm.del...@gmail.com> wrote: > >> > >> >On Sunday, January 15, 2023 at 12:10:54 AM UTC-4, John Larkin wrote: > >> >> On Sat, 14 Jan 2023 17:52:45 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> <gnuarm.del...@gmail.com> wrote: > >> >> > >> >> >On Saturday, January 14, 2023 at 9:34:09 PM UTC-4, John Larkin wrote: > >> >> >> On Sat, 14 Jan 2023 16:20:53 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> >> <gnuarm.del...@gmail.com> wrote: > >> >> >> > >> >> >> >On Saturday, January 14, 2023 at 3:17:24 PM UTC-4, John Larkin wrote: > >> >> >> >> On Sat, 14 Jan 2023 10:05:33 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> >> >> <gnuarm.del...@gmail.com> wrote: > >> >> >> >> > >> >> >> >> >On Saturday, January 14, 2023 at 12:08:03 PM UTC-4, John Larkin wrote: > >> >> >> >> >> On Fri, 13 Jan 2023 21:20:50 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: > >> >> >> >> >> > >> >> >> >> >> >On Saturday, January 14, 2023 at 12:39:49 AM UTC-4, John Larkin wrote: > >> >> >> >> >> >> On Sat, 7 Jan 2023 09:49:24 -0800 (PST), "gnuarm.del...@gmail.com" > >> >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: > >> >> >> >> >> >> > >> >> >> >> >> >> >A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! > >> >> >> >> >> >> > > >> >> >> >> >> >> >So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find that fit on the board have 196 or 256 pins. But the real problem is availability. > >> >> >> >> >> >> > > >> >> >> >> >> >> >Digikey has a few of the XC7S15-1FTGB196I and more a scheduled for delivery in April. Add in the various speed and temperature flavors trickling in (mostly in April) and I should be ok for the initial delivery in August... if I can get my hands on those. I don't know if Digikey factors in the backlog orders in these counts. > >> >> >> >> >> >> > > >> >> >> >> >> >> >Mouser shows great inventory of Efinix parts, particularly the T13 and T20 in a 0.8 mm 256 pin BGA, 10s of thousands in stock. But I'd rather work with a 1.0 mm BGA. Oddly enough, LCSC shows part numbers, but zero inventory. > >> >> >> >> >> >> > > >> >> >> >> >> >> >Anyone work with 0.8 mm BGAs? What PWB feature dimensions did you use? Did this impact the PWB cost? > >> >> >> >> >> >> The 0.8 mm 256-ball T20 isn't bad... > >> >> >> >> >> >> > >> >> >> >> >> >> https://www.dropbox.com/s/xjqgj2pz9mdhtma/P941_FPGA.jpg?raw=1 > >> >> >> >> >> > > >> >> >> >> >> >I can't really see much detail. It looks like there are virtually no pads on the vias under the BGA. What size are they? > >> >> >> >> >> The BGAVIAs are 12.5 mil OD with 8 mil drills. The other vias on the > >> >> >> >> >> board STANDARDVIA and POWERVIA are bigger. > >> >> >> >> > > >> >> >> >> >2.25 mil (0.057 mm) is a pretty narrow via ring. Why not have a larger via pad? > >> >> >> >> I don't know. My PCB guy decides stuff like that. I'd guess that he > >> >> >> >> wanted it to pass some design rule check, or maybe he started metric. > >> >> >> >> The board houses haven't complained as far as I know. > >> >> >> >> > >> >> >> >> You should do your own thing and check with whoever will make your > >> >> >> >> boards. > >> >> >> > > >> >> >> >Sounds good, but I've never been able to get a board house to even discuss these issues. They always take the approach that they will work with what I give them, which means, if it gives poor results, it's my problem. > >> >> >> We always specify bare-board testing and warpage and tolerances, so we > >> >> >> don't get bad boards. What we can get is expensive boards. > >> >> >> > > >> >> >> >There are a number of board companies with published capabilities, but they all vary, enough that there seems to be no consensus. Just like your via pad size. I've never seen a board house that says that would be a standard board. I was just looking at one company who wants 10 mil annular ring on inner layers and 7 mil annular ring on surface layers. That's a huge difference from 2.25 mil. On the other hand, they will print 2.5 mil trace/space! > >> >> >> Zero annular ring seems to be OK on inners. That reduces capacitance. > >> >> >> 5 or even 4 mil traces are usually standard price. I don't know why my > >> >> >> guy used 6 on the board that I posted. > >> >> >> > >> >> >> We do email our board houses and often they answer! > >> >> > > >> >> >You aren't paying attention. > >> >> That's because you're obnoxious. > >> > > >> >Wow! Talk about sensitive. What is going on with you??? > >> Just trying to help. My mistake. > > > >Dude, you are way too sensitive. Chillax! You'll live longer. > Stop being obnoxious and you'll get more help. > > But not fom me.I'm not going to continue to argue. Thank you for your opinions on using BGAs. But the price of your comments is too high. People have to walk on tiptoes around you to avoid insulting you. Sorry, but I left my ballet shoes in the car. I would hope that someday, you might get some help with this issue. In the meantime, you are not the only electronic designer in the world. Other people design "things that work", every day. Bye, -- Rick C. -+-+ Get 1,000 miles of free Supercharging -+-+ Tesla referral code - https://ts.la/richard11209
Reply by ●January 17, 20232023-01-17
On Mon, 16 Jan 2023 07:29:10 -0800 (PST), "gnuarm.del...@gmail.com" <gnuarm.deletethisbit@gmail.com> wrote:>On Monday, January 16, 2023 at 11:04:28 AM UTC-4, John Larkin wrote: >> On Sun, 15 Jan 2023 20:11:34 -0800 (PST), "gnuarm.del...@gmail.com" >> <gnuarm.del...@gmail.com> wrote: >> >> >On Sunday, January 15, 2023 at 2:37:04 PM UTC-4, John Larkin wrote: >> >> On Sat, 14 Jan 2023 21:04:55 -0800 (PST), "gnuarm.del...@gmail.com" >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >On Sunday, January 15, 2023 at 12:10:54 AM UTC-4, John Larkin wrote: >> >> >> On Sat, 14 Jan 2023 17:52:45 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >On Saturday, January 14, 2023 at 9:34:09 PM UTC-4, John Larkin wrote: >> >> >> >> On Sat, 14 Jan 2023 16:20:53 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >On Saturday, January 14, 2023 at 3:17:24 PM UTC-4, John Larkin wrote: >> >> >> >> >> On Sat, 14 Jan 2023 10:05:33 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >> >> >On Saturday, January 14, 2023 at 12:08:03 PM UTC-4, John Larkin wrote: >> >> >> >> >> >> On Fri, 13 Jan 2023 21:20:50 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >> >> >> >> >On Saturday, January 14, 2023 at 12:39:49 AM UTC-4, John Larkin wrote: >> >> >> >> >> >> >> On Sat, 7 Jan 2023 09:49:24 -0800 (PST), "gnuarm.del...@gmail.com" >> >> >> >> >> >> >> <gnuarm.del...@gmail.com> wrote: >> >> >> >> >> >> >> >> >> >> >> >> >> >> >A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! >> >> >> >> >> >> >> > >> >> >> >> >> >> >> >So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find that fit on the board have 196 or 256 pins. But the real problem is availability. >> >> >> >> >> >> >> > >> >> >> >> >> >> >> >Digikey has a few of the XC7S15-1FTGB196I and more a scheduled for delivery in April. Add in the various speed and temperature flavors trickling in (mostly in April) and I should be ok for the initial delivery in August... if I can get my hands on those. I don't know if Digikey factors in the backlog orders in these counts. >> >> >> >> >> >> >> > >> >> >> >> >> >> >> >Mouser shows great inventory of Efinix parts, particularly the T13 and T20 in a 0.8 mm 256 pin BGA, 10s of thousands in stock. But I'd rather work with a 1.0 mm BGA. Oddly enough, LCSC shows part numbers, but zero inventory. >> >> >> >> >> >> >> > >> >> >> >> >> >> >> >Anyone work with 0.8 mm BGAs? What PWB feature dimensions did you use? Did this impact the PWB cost? >> >> >> >> >> >> >> The 0.8 mm 256-ball T20 isn't bad... >> >> >> >> >> >> >> >> >> >> >> >> >> >> https://www.dropbox.com/s/xjqgj2pz9mdhtma/P941_FPGA.jpg?raw=1 >> >> >> >> >> >> > >> >> >> >> >> >> >I can't really see much detail. It looks like there are virtually no pads on the vias under the BGA. What size are they? >> >> >> >> >> >> The BGAVIAs are 12.5 mil OD with 8 mil drills. The other vias on the >> >> >> >> >> >> board STANDARDVIA and POWERVIA are bigger. >> >> >> >> >> > >> >> >> >> >> >2.25 mil (0.057 mm) is a pretty narrow via ring. Why not have a larger via pad? >> >> >> >> >> I don't know. My PCB guy decides stuff like that. I'd guess that he >> >> >> >> >> wanted it to pass some design rule check, or maybe he started metric. >> >> >> >> >> The board houses haven't complained as far as I know. >> >> >> >> >> >> >> >> >> >> You should do your own thing and check with whoever will make your >> >> >> >> >> boards. >> >> >> >> > >> >> >> >> >Sounds good, but I've never been able to get a board house to even discuss these issues. They always take the approach that they will work with what I give them, which means, if it gives poor results, it's my problem. >> >> >> >> We always specify bare-board testing and warpage and tolerances, so we >> >> >> >> don't get bad boards. What we can get is expensive boards. >> >> >> >> > >> >> >> >> >There are a number of board companies with published capabilities, but they all vary, enough that there seems to be no consensus. Just like your via pad size. I've never seen a board house that says that would be a standard board. I was just looking at one company who wants 10 mil annular ring on inner layers and 7 mil annular ring on surface layers. That's a huge difference from 2.25 mil. On the other hand, they will print 2.5 mil trace/space! >> >> >> >> Zero annular ring seems to be OK on inners. That reduces capacitance. >> >> >> >> 5 or even 4 mil traces are usually standard price. I don't know why my >> >> >> >> guy used 6 on the board that I posted. >> >> >> >> >> >> >> >> We do email our board houses and often they answer! >> >> >> > >> >> >> >You aren't paying attention. >> >> >> That's because you're obnoxious. >> >> > >> >> >Wow! Talk about sensitive. What is going on with you??? >> >> Just trying to help. My mistake. >> > >> >Dude, you are way too sensitive. Chillax! You'll live longer. >> Stop being obnoxious and you'll get more help. >> >> But not fom me. > >I'm not going to continue to argue. Thank you for your opinions on using BGAs. But the price of your comments is too high. People have to walk on tiptoes around you to avoid insulting you. Sorry, but I left my ballet shoes in the car. > >I would hope that someday, you might get some help with this issue. In the meantime, you are not the only electronic designer in the world. Other people design "things that work", every day. > >Bye,Oh, are you the rick from SED? I should have noticed. Bye indeed.
Reply by ●January 27, 20232023-01-27
Am 07.01.2023 um 18:49 schrieb gnuarm.del...@gmail.com:> A small board with a 100QFP is being redesigned for a new FPGA due to obsolescence. Gowin makes a 100QFP device that would be a good fit, but my customer has said "no" to the 100% Chinese brand... US government customers, ya know! > > So now I'm looking at a BGA. I don't want to get into fine PCB design rules, so 1.0 mm ball pitch is my preference. The only devices I can find that fit on the board have 196 or 256 pins. But the real problem is availability. > > Digikey has a few of the XC7S15-1FTGB196I and more a scheduled for delivery in April. Add in the various speed and temperature flavors trickling in (mostly in April) and I should be ok for the initial delivery in August... if I can get my hands on those. I don't know if Digikey factors in the backlog orders in these counts. > > Mouser shows great inventory of Efinix parts, particularly the T13 and T20 in a 0.8 mm 256 pin BGA, 10s of thousands in stock. But I'd rather work with a 1.0 mm BGA. Oddly enough, LCSC shows part numbers, but zero inventory. > > Anyone work with 0.8 mm BGAs? What PWB feature dimensions did you use? Did this impact the PWB cost? >I've done a 324pin 0.8mm BGA recently. My PCB fab is: https://www.multi-circuit-boards.eu/en/index.html, they also have a german office near my house. I used all standard parameters like 0.2mm holes, 0.4mm via diameters and 0.1mm trace width and spaces on a 6-layer board, GND at layers 2 and 5. Power planes are used on layer 3, as well as additional power and signal routing. All was manufactured perfectly fine and the board works as expected. I was the schematics developer as well as the layouter. There are some optimazations you can do if you do both. You can try to join several pwr pins to one via and then get the space for placing 0402 capacitors under the BGA. (Recommended is max. 2 BGA-pads to one via) Using 0201 caps saves you from doing tricky via omitting. Using 0204 caps did't help in my case. You can also ignore some I/Os for routing critical high speed nets. There is lots of room for playing around optimizing and finally you can use all BGA-pads. I used Altium and partly it was a fun job as well as a mess with length matching. Doing 0.8mm is an easy job IMHO, also have done some 1mm BGAs, then used 0.5mm via diameter. The advantage of using 2 tracks between 2 balls is not too big. A 1mm 196ball FPGA has the same size as a 324pin 0.8mm chip, 15x15mm. And now how to assemble a BGA pcb ? Look here: https://www.youtube.com/watch?v=EMCz0VsEbqc Mike PS: Xilinx recommends lots of caps in power distribution network however on the eval boards like SP701, AC701 and others these caps are placed centimeters away from the chip... -- Mike Randelzhofer, OHO-Elektronik
Reply by ●January 27, 20232023-01-27
On Friday, January 27, 2023 at 12:39:16 PM UTC-4, Mike Randelzhofer wrote:> Am 07.01.2023 um 18:49 schrieb gnuarm.del...@gmail.com:=20 > > A small board with a 100QFP is being redesigned for a new FPGA due to o=bsolescence. Gowin makes a 100QFP device that would be a good fit, but my c= ustomer has said "no" to the 100% Chinese brand... US government customers,= ya know!=20> >=20 > > So now I'm looking at a BGA. I don't want to get into fine PCB design r=ules, so 1.0 mm ball pitch is my preference. The only devices I can find th= at fit on the board have 196 or 256 pins. But the real problem is availabil= ity.=20> >=20 > > Digikey has a few of the XC7S15-1FTGB196I and more a scheduled for deli=very in April. Add in the various speed and temperature flavors trickling i= n (mostly in April) and I should be ok for the initial delivery in August..= . if I can get my hands on those. I don't know if Digikey factors in the ba= cklog orders in these counts.=20> >=20 > > Mouser shows great inventory of Efinix parts, particularly the T13 and =T20 in a 0.8 mm 256 pin BGA, 10s of thousands in stock. But I'd rather work= with a 1.0 mm BGA. Oddly enough, LCSC shows part numbers, but zero invento= ry.=20> >=20 > > Anyone work with 0.8 mm BGAs? What PWB feature dimensions did you use? =Did this impact the PWB cost?=20> > > I've done a 324pin 0.8mm BGA recently.=20 >=20 > My PCB fab is:=20 >=20 > https://www.multi-circuit-boards.eu/en/index.html,=20 >=20 > they also have a german office near my house.=20 >=20 > I used all standard parameters like 0.2mm holes, 0.4mm via diameters and==20> 0.1mm trace width and spaces on a 6-layer board, GND at layers 2 and 5.==20> Power planes are used on layer 3, as well as additional power and signal==20> routing.=20 >=20 > All was manufactured perfectly fine and the board works as expected.=20 >=20 > I was the schematics developer as well as the layouter.=20 >=20 > There are some optimazations you can do if you do both.=20 > You can try to join several pwr pins to one via and then get the space=20 > for placing 0402 capacitors under the BGA.=20 > (Recommended is max. 2 BGA-pads to one via)=20 >=20 > Using 0201 caps saves you from doing tricky via omitting.=20 > Using 0204 caps did't help in my case.=20 >=20 > You can also ignore some I/Os for routing critical high speed nets.=20 >=20 > There is lots of room for playing around optimizing and finally you can==20> use all BGA-pads.=20 > I used Altium and partly it was a fun job as well as a mess with length==20> matching.=20 >=20 > Doing 0.8mm is an easy job IMHO, also have done some 1mm BGAs, then used==20> 0.5mm via diameter.=20 > The advantage of using 2 tracks between 2 balls is not too big.=20 > A 1mm 196ball FPGA has the same size as a 324pin 0.8mm chip, 15x15mm.=20 >=20 > And now how to assemble a BGA pcb ?=20 > Look here:=20 > https://www.youtube.com/watch?v=3DEMCz0VsEbqc=20 >=20 > Mike=20 >=20 > PS:=20 > Xilinx recommends lots of caps in power distribution network however on==20> the eval boards like SP701, AC701 and others these caps are placed=20 > centimeters away from the chip...=20 >=20 > --=20 > Mike Randelzhofer, OHO-ElektronikThanks for the info. That was a very good explanation/description. I have= been considering 0402 as well as 0201 parts. I don't have high speed sig= nals. This is a redo from 2008 and a couple of EOL parts, including the FP= GA. If the part was still available, I would be using a 100TQFP. =20 I would like to use the 196 pin, 1 mm pitch Xilinx part, but while there ar= e just enough parts in inventory (in various speed/temperatures) to do the = initial order, further quantities are a year away. If it were a slightly m= ore perfect world, I'd probably go with an XC7S part. The XC7S6 would prob= ably do the job ok, but I'd want to bump up to the XC7S15 just to have clea= r breathing room. I think the parts are footprint compatible, so if I want= to save the $5, I could always switch at a different time. Interesting th= at there's only 100 I/Os available in a 196 ball package, no matter which d= ie is in it! =20 Most likely, I'm going with the Efinix T20. That cuts the FPGA cost in hal= f! I just have to work with 0.8 mm ball pitch. Again, I could probably us= e a T13, but Efinix uses cells for routing, so I'm very unclear as to the b= est size and, again, very little difference in price. Also, 195 I/Os! Don= 't need them on the product board, but I also am building a test fixture, w= here I'll use the same part and the extra I/Os help a lot!=20 --=20 Rick C. -++- Get 1,000 miles of free Supercharging -++- Tesla referral code - https://ts.la/richard11209
Reply by ●January 27, 20232023-01-27
The remaining problem I'm having, is the op amps I use to drive the outputs. They need to drive 50 ohm loads, single ended, or 600 ohm, differential, from a single 12V supply. The LM8272 parts I picked 14 years ago, are uniquely qualified for the high current output, 12V supply and MSOP8 package. Unfortunately, they have a 1 year lead time and virtually none in distribution, other than no name outfits from overseas. The board is very small and crowded. Everything I've tried to replace them with is either too large, or isn't rated for 12V power, or just won't drive the current. I ran through the analysis again, and I just can't find a better part. The circuit I'm using uses positive feedback to make a 12.1 ohm output resistor look like a 50 ohm output impedance, from a higher V+. Works the champ. Looking at the typical I/V output curve, it will drive 80 mA into the 62.1 ohm load with 8 Vpp on the 50 ohm load. Of course, that's a typical number, not a spec, but this is what we are selling now and the customer is happy with it. So I want to give them the same thing. What really surprises me, is that headphone amps (which should be perfect for this) are made to run from 5V only and higher power devices are mostly class D, which would need large inductors to smooth out the carrier frequency (large for this board). It's hard to find anything class AB that will run on a 12V supply. -- Rick C. -+++ Get 1,000 miles of free Supercharging -+++ Tesla referral code - https://ts.la/richard11209
Reply by ●January 28, 20232023-01-28
On 27/01/2023 17:39, Mike Randelzhofer wrote:> > PS: > Xilinx recommends lots of caps in power distribution network however on > the eval boards like SP701, AC701 and others these caps are placed > centimeters away from the chip... >As long as the path between the bypass caps and the power balls is low inductance (i.e., minimal paths then vias to power polygons) and low DC impedance (i.e., power polygons covering the caps and the device itself), there's no problem being centimetres away. If I remember my numbers correctly, at 100 MHz a tenth of the wavelength will be about 5cm, so placing closer than that gives no benefits. Details can vary depending on your needs, of course - if you have a lot of hard high-power simultaneous switching at higher frequencies then you need to be much more careful with bypassing than if it is more spread out.
