Virtex4 FX12 dynamic clock divider

I found DDS code in comp.arch.fpga archives:

library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity dds is
 generic(
    bits:natural);
 port(
  clk: in std_logic;
  inc: out std_logic_vector;
  clk_out: out std_logic);

end dds;

architecture RTL of dds is
    signal accum unsigned(bits-1 downto 0);
begin

process(clk)
begin
    if clk'event and clk='1' then
        accum<=accum+unsigned(inc);
    end if;
end process;
clk_out<=accum(bits-1);

end RTL;


Re: Falk: Good indea about bidirectional port. I am using Virtex-4 FX12
SF363 -10.

Thnx, Guru

Guru wrote:
> Here are some more details:
> Desired clock increment is about 1 MHz.
> Maximum jitter not specified.
> 2 DCMs free for now.
>
> I think that DCM with dynamic FX ratios cannot produce such increments,

Guru,

A five minute exercise with an excel spreadsheet is all it takes to
come up with the answer to the DCM resolution question.  If starting
with a 66MHz input clock (which from the exercise became clear to me
that one would want to use the top frequency of the range to get best
resolution), you can get very close to your desired resolution.  There
will be steps of 1.06MHz going from M/D of 15/31 to 1/2 and from 1/2 to
16/31, so the worst two steps happen to be adjacent, and at the very
low end of your frequency range.  The next worst step pairs are
0.76MHz, 0.71MHz, and 0.53MHz and 0.57MHz.

The interesting thing to note is that the steps immediately prior and
immediately after each of the worst case pairs are all on the order of
0.10MHz.  So as a practical matter the DCM gets you extremely close.
If your range of frequencies were just slightly less than 2:1 (i.e.
34MHz to 66MHz) you would be able to get a worst case 0.76MHz step
size.

The DCM solution will drastically reduce the jitter.  This may or may
not be significant in your application.  The M/D values will want to be
stored in a look up table (i.e. a blockram).

Just more food for thought.


Regards,
Erik.

---
Erik Widding
President
Birger Engineering, Inc.

 (mail) 100 Boylston St #1070; Boston, MA 02116
(voice) 617.695.9233
  (fax) 617.695.9234
  (web) http://www.birger.com

Thanks Erik,

I did my homework:

DDFS at 300MHz using DDR primitive has 1.67ns of jitter.
The DDFS problem are high frequencies, where 1.67ns of resolution
results in 66.6 to 60 increment (15 to 16.6ns). This is the are where I
need the finest resolution.
Another problem is building from a scratch - it takes lots of time.

I will use DCM_ADV solution with dynamic M/D. With one DCM I will
produce 66.66MHz (100*4/6) which will be used as an input clock of
DCM_ADV. To simplify the design I will lock the divider D to 32 (input
31) and change only the multiplier value from 12 to 32 (25 to 66.6
MHz). In this way I get 2.083MHz resolution (which I think is enough)
in the whole range and only 0.5ns of jitter (according to Xilinx
LogiCore calculation).
>From my opinion this the best solution for the purpose.

Thank you all,

Guru