Verilog vs VHDL

Kishore  wrote
> -> Are there things that VHDL does better than verilog or vice-versa

It's is much easier to calculate constraints (LOCs and the like) in VHDL. 
Only applies if you need to do higher performance stuff, when it becomes 
100% vital, IMHO.

And VHDL is tougher on types, saving some debugging time.

I'm not an expert, but I believe the latest Verilog has caught up with VHDL 
on generate, etc.

In article <1148420806.519398.325680@u72g2000cwu.googlegroups.com>,
Kishore <kishore2k4@gmail.com> wrote:
>Hi,
>
>     I know this has been brought up many times in various groups but
>here is my view on them and I would really appreciate some
>clarification. I started working on FPGA design and stuff some 3 months
>back or so. All the time I was switching back and forth between verilog
>and VHDL for various projects. I personally feel that one can be very
>productive as in time with Verilog? I only use VHDL if there is no
>choice but I am not aganist VHDL or anything.
>
>     After some searching on google and various usenet groups I came
>across many arguments regarding Verilog vs VHDL  summarising either as
>"use the right the tool for the right job" or "leading to language
>wars". I am open-minded and I am biased to the former at the same time
>a bit biased to verilog :) I just wanted to know some things.
>
>-> Are there things that VHDL does better than verilog or vice-versa
>-> What is the most widely used language in the industry i.e. FPGA and
>ASIC designs. I think VHDL is the dominant one as Xilinx totally uses
>VHDL?
>
>   All kinds of thoughts, experiences and constructive criticisms will
>be helpful.


Here be dragons and I should perhaps not jump into the dragon pit, but 
here's an observation:

One thing I notice is that people who have had exposure to software 
development seem to prefer VHDL because VHDL allows one to define new 
types whereas with Verilog you've gotta be happy with the types that come 
with it out-of-the-box.  Hardware engineers with lots of software 
background might therefore tend to prefer VHDL whereas Hardware engineers 
with less software development experience might tend to prefer Verilog 
because they may not care about the potential benefits of being able to  
define new types.

...but I don't want to over generalize... ;-)

Phil

I think it just goes way back to when Verilog first came out, we were
still driven by schematics in the early 80s, the nested symbol was the
level of abstraction used.

Verilog was primary invented by Moorby when he joined Gateway. On day
one he was told they had a synthesis tool with no language to drive it,
so he insisted on building one. He had previously built the Hilo tool
for Genrad so he had a good insight as to what was needed at that time.

It may be true that in the past hardware guys with little software
experience didn't care about having such abstractions available since
the divide was far greater then, but the opposite point can't always be
true. When you are proficient in software and hardware you can still
choose Verilog over VHDL because the missing abstractions can be got by
working in C or other languages. Most projects involve both hardware &
software and Verilog + something else was able to make up for the
missing features that VHDL had.

I wonder what programming  languages VHDL fans generally favor, is it
just same as everyone else? Does VHDL generally need C or anything to
boost it in anyway?

John Jakson
transputer guy

In article <1148510875.580909.76090@y43g2000cwc.googlegroups.com>,
JJ <johnjakson@gmail.com> wrote:
>I think it just goes way back to when Verilog first came out, we were
>still driven by schematics in the early 80s, the nested symbol was the
>level of abstraction used.
>
>Verilog was primary invented by Moorby when he joined Gateway. On day
>one he was told they had a synthesis tool with no language to drive it,
>so he insisted on building one. He had previously built the Hilo tool
>for Genrad so he had a good insight as to what was needed at that time.
>
>It may be true that in the past hardware guys with little software
>experience didn't care about having such abstractions available since
>the divide was far greater then, but the opposite point can't always be
>true. When you are proficient in software and hardware you can still
>choose Verilog over VHDL because the missing abstractions can be got by
>working in C or other languages. Most projects involve both hardware &
>software and Verilog + something else was able to make up for the
>missing features that VHDL had.

Well, C doesn't exactly offer a lot of abstraction either...

>
>I wonder what programming  languages VHDL fans generally favor, is it
>just same as everyone else? 


I like Ruby for lots of things and I'm learning Io, functional 
programming. Lisp/Scheme are cool too.

> Does VHDL generally need C or anything to
>boost it in anyway?

While I refer VHDL over Verilog, VHDL is still lacking...

Phil

Phil Tomson wrote:
> Here be dragons and I should perhaps not jump into the dragon pit, but 
> here's an observation:
> 
> One thing I notice is that people who have had exposure to software 
> development seem to prefer VHDL 

As a retired computer programmer of 35+ years who has only recently 
taught myself Verilog during my retirement (as a hobby), I vastly prefer 
Verilog to what I've seen of VHDL.

On the other hand, most of my programming was "down to the metal" device 
drivers and realtime embedded systems work, so it was very important for 
me to be able to easily deal with hardware interfaces and to know 
exactly what code the compiler (if used at all) generated so I could 
have strict control over the timing of things. I was overjoyed when the 
C programming language came along because it maps very well to the 
computer architectures of most machines and allowed me to use a high 
level language instead of assembly language even when doing 
bit-twiddling things such as device drivers (I had used assembly and 
Pascal up until then). The transition from C to Verilog was almost 
totally painless once I figured out this new concept of "wires" ;-) 
because of the similarity between the two languages - at least as far as 
the low level operators and general design philosophy of the languages go.

The thing that bothers me most about abstract computer languages such as 
COBOL,  Lisp, ADA, and I will include VHDL in this category) is that the 
hardware the design is implemented on is *not* abstract at all - it is 
composed of bits and bytes and elementary operations an ALU can perform, 
and so if I care anything at all about performance I like to use a 
relatively low level language.

I think it's rather amusing that whenever I do a new Verilog design, I 
usually begin by coding the algorithm in the Maple computer language. 
Maple is a very high level arbitrary precision language that can do 
symbolic algebra, calculus, differential equations, etc. It may be a 
surprising choice as a design language for Verilog, but it works quite 
well because Maple allows me to do pretty much whatever I want without 
regard to implementation specifics. When I wrote the Verilog 
implementation of Lenstra's Elliptic Curve Factoring method (ECM), I 
started by writing a Maple program from the algorithm described in a 
textbook, and then gradually decomposed each of the higher level 
operations into simpler operations until I had something that could be 
implemented easily in Verilog. :-)

Ron


P.S.
My Verilog ECM factoring design for the RSA-704 challenge number is now 
in its 178'th hour of synthesis (CPU hours), and shows no signs of 
finishing any time soon. I'm using Xilinx 5.1 Foundation software 
targeted at a Xilinx XCV2000E FPGA, and running on a Pentium 4 with 1.5 
GB of RAM.

Ron <News5@spamex.com> writes:

> The thing that bothers me most about abstract computer languages such
> as COBOL,  Lisp, ADA, and I will include VHDL in this category) is
> that the hardware the design is implemented on is *not* abstract at
> all - it is composed of bits and bytes and elementary operations an
> ALU can perform, and so if I care anything at all about performance I
> like to use a relatively low level language.
> 

The thing about VHDL is that although it has some highish levels of
abstraction, which are great for the test environment.  However, if
you are writing synthesisable code, you are much more constrained, and
the language maps relatively predictably (most of the time) onto
device hardware.  So you get the best of both worlds.  

IMHO There's no *design performance* reason to prefer Verilog over
VHDL.  At the RTL level they are pretty much equivalent nowadays (as I
understand it, I'm predominantly a VHDL man myself)

> I think it's rather amusing that whenever I do a new Verilog design, I
> usually begin by coding the algorithm in the Maple computer
> language. Maple is a very high level arbitrary precision language that
> can do symbolic algebra, calculus, differential equations, etc. It may
> be a surprising choice as a design language for Verilog, but it works
> quite well because Maple allows me to do pretty much whatever I want
> without regard to implementation specifics. When I wrote the Verilog
> implementation of Lenstra's Elliptic Curve Factoring method (ECM), I
> started by writing a Maple program from the algorithm described in a
> textbook, and then gradually decomposed each of the higher level
> operations into simpler operations until I had something that could be
> implemented easily in Verilog. :-)
> 

That's always a good way to proceed :-)

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt  
   

Ron wrote:
> As a retired computer programmer of 35+ years who has only recently
> taught myself Verilog during my retirement (as a hobby), I vastly prefer
> Verilog to what I've seen of VHDL.


I dont unstand what you are saying, Ron.
You are a Verilog novice and don't know VHDL.  You may have 35+ years
of "experience", but that doesn't make you more credible in this
particular context

> On the other hand, most of my programming was "down to the metal" device
> drivers and realtime embedded systems work, so it was very important for
> me to be able to easily deal with hardware interfaces and to know
> exactly what code the compiler (if used at all) generated so I could
> have strict control over the timing of things. I was overjoyed when the
> C programming language came along because it maps very well to the
> computer architectures of most machines and allowed me to use a high
> level language instead of assembly language even when doing
> bit-twiddling things such as device drivers (I had used assembly and
> Pascal up until then). The transition from C to Verilog was almost
> totally painless once I figured out this new concept of "wires" ;-)
> because of the similarity between the two languages - at least as far as
> the low level operators and general design philosophy of the languages go.

If your C and Verilog are very close to each other, then something is
very wrong.
Ignoring the HW vs SW-mind, yes the syntax is kind of resembling. But
after 35+ years you should be able to learn any syntax in a day or two?

Do you seriously mean that you choose Verilog over VHDL because you
couldn't learn to write "AND" instead of "&"?

(BTW, I am a C programmer by trade. Wondering my favourite HDL? read on
then...)

>
> The thing that bothers me most about abstract computer languages such as
> COBOL,  Lisp, ADA, and I will include VHDL in this category) is that the
> hardware the design is implemented on is *not* abstract at all - it is

*Everything* is abstract, at some level and with some distance...

If you haven't seen it yet, its because you are playing with tiny
designs (knowning your answer here, I counter: yes, you can still fill
a large FPGA with a tiny design).
And for gods sake, how did you - as a software guy - missed the big
"abstraction wave" during the 90s?


> composed of bits and bytes and elementary operations an ALU can perform,
> and so if I care anything at all about performance I like to use a
> relatively low level language.

You said you prefer C over assembler. Well, same thing here. Please
read up on behavioural-but-still-synthesizable-code.

Given the current state of synthesis tools, I prefer to write code at a
higher level and let Synplify/DC/Leonardo/Quartus/Blast/Palace do their
magic. Somehow, I don't feel like doing multimillion-gate designs at
transistor  level.


>
> I think it's rather amusing that whenever I do a new Verilog design, I
> usually begin by coding the algorithm in the Maple computer language.
> Maple is a very high level arbitrary precision language that can do
> symbolic algebra, calculus, differential equations, etc. It may be a
> surprising choice as a design language for Verilog, but it works quite
> well because Maple allows me to do pretty much whatever I want without

Now you are contradicting yourself. I use C-based languages
(C/C++/Java/C#/..) to prototype.
I may use Matlab when I do DSP, but thats another story.

> regard to implementation specifics. When I wrote the Verilog
> implementation of Lenstra's Elliptic Curve Factoring method (ECM), I
> started by writing a Maple program from the algorithm described in a
> textbook, and then gradually decomposed each of the higher level
> operations into simpler operations until I had something that could be
> implemented easily in Verilog. :-)


I know VHDL, Verilog and SystemC plus a few more (there were tons of
other languages during the PAL/PLD-era). And believe me, they are all
pretty much the same, SPECIALLY AT LOW-LEVEL!

>From my experience, people recommending language V1 over another
language V2 do it because they don't know language V2.
Given that VHDL is a bit harder to learn, you hear a lot of this from
the Verilog-Only camp.
And then you have the ASIC people who love to hate VHDL. But Austin and
Peter say ASIC is dying, and given that they are one of world largest
AISC shops I assume they know what they are talking about :)

Ok back to the subject, if you are serious about HW design, you MUST
know at least VHDL and Verilog. Well, unless you never ever use
IP-blocks, which is a whole another discussion...

All,

Lately I got a database of ICs, analog, digital, etc. market research.

It allows you to ask questions like:

"Who are the top 5 digital logic IC companies, in order of 1 to 5, and
how did they fare compared to last year (2005 vs 2004)"

Intel +27.2% up from last year to 10.3% of market
Qualcomm up 7.5% with 5.4% of market
Broadcomm up 10.4% with 5.4%
nVidia up 23.8% with 4.4%
and
ATI up 6% with 4.4%

Which makes those top 5 with only 29.8% of the total market, but with
$14.21 billion in revenues from all Logic ICs.  This is everyone.  Us
included.

But, since that is not so narrow as just ASICs, I then narrowed it to
Logic ASICs:

IBM down 8% with 15.7% of market
Fujitsu down 3.8% with 10.7%
NEC down 26.8% with 9% of market
Toshiba even with 6.4% of market
and
Agere down 3.1% with 6.3% of market

Which makes for 48.1% of the market, which comprises $5.9 billion (total
logic ASIC here is $12.34 down 7.2% from last year.

Looking at PLDs alone (no surprises here):

Xilinx up 3.7% with 50.3%
Altera up 7.6% with 33.1%
Lattice down 7.1% with 6.4%
Actel up 7.8% with 5.5%
and
QuickLogic up 6.7% with 1.5%

Which makes these 5 with 96.8% of a $3.17 billion market, which overall
grew 3.6% over last year.


Hmmm.  Logic ASIC ~4X PLD's ...that's interesting.


So, what happens when you combine the Logic ASIC with the PLD markets,
and look at them together?

IBM down 8% with 12.4%
Xilinx up 3.7% with 10.5%
Fujitsu down 3.8% with 8.4%
Altera up 10.6% with 7.2%
and
NEC down 26.8% with 7.1%

A combined 45.7% of the total market, which accounts for $7.13 billion.


Conclusion:

So, if you are wondering if you should learn verilog or VHDL, the
figures really say you should know both.  Well.  Really well.

Austin

Austin Lesea (austin@xilinx.com) wrote:
: All,

: So, if you are wondering if you should learn verilog or VHDL, the
: figures really say you should know both.  Well.  Really well.

(Going of on a tanget here from the bulk of Austin's posting...!)

Hah.  I get a bit bored seeign the repetative 'Should I learn VHDL or
Verilog' questions.  Both are a bit more nebulous than most software 
languages people learn, in that everyone's synthesis or simulation
tools implement different parts of the language spec for different
purposes, and ultimatly most people on CAF use them to describe what they
want a CPLD/FPGA to do.  Chuck in the mess of things like VHDL attributes
and Verilog comments being used to pass (vendor / technology) specific hints
to the synthesiser...

When that's the case what you really need to know is what you want the
device to do, how the device works best, and the intersection between the
two.  If you've got half a clue about that and are competent in any 
computer language then VHDL/Verilog become little more than a preference
for a syntax (other than generate + attributes etc. in rare cases.)

And both could be much better.  Much much better.  Oh well...

cds

Austin Lesea wrote:

> All,
> 
> Lately I got a database of ICs, analog, digital, etc. market research.
> 
> It allows you to ask questions like:
> 
> "Who are the top 5 digital logic IC companies, in order of 1 to 5, and
> how did they fare compared to last year (2005 vs 2004)"
> 
> Intel +27.2% up from last year to 10.3% of market
> Qualcomm up 7.5% with 5.4% of market
> Broadcomm up 10.4% with 5.4%
> nVidia up 23.8% with 4.4%
> and
> ATI up 6% with 4.4%
> 
> Which makes those top 5 with only 29.8% of the total market, but with
> $14.21 billion in revenues from all Logic ICs.  This is everyone.  Us
> included.
> 
> But, since that is not so narrow as just ASICs, I then narrowed it to
> Logic ASICs:
> 
> IBM down 8% with 15.7% of market
> Fujitsu down 3.8% with 10.7%
> NEC down 26.8% with 9% of market
> Toshiba even with 6.4% of market
> and
> Agere down 3.1% with 6.3% of market
> 
> Which makes for 48.1% of the market, which comprises $5.9 billion (total
> logic ASIC here is $12.34 down 7.2% from last year.
> 
> Looking at PLDs alone (no surprises here):
> 
> Xilinx up 3.7% with 50.3%
> Altera up 7.6% with 33.1%
> Lattice down 7.1% with 6.4%
> Actel up 7.8% with 5.5%
> and
> QuickLogic up 6.7% with 1.5%
> 
> Which makes these 5 with 96.8% of a $3.17 billion market, which overall
> grew 3.6% over last year.
> 
> 
> Hmmm.  Logic ASIC ~4X PLD's ...that's interesting.
> 
> 
> So, what happens when you combine the Logic ASIC with the PLD markets,
> and look at them together?
> 
> IBM down 8% with 12.4%
> Xilinx up 3.7% with 10.5%
> Fujitsu down 3.8% with 8.4%
> Altera up 10.6% with 7.2%
> and
> NEC down 26.8% with 7.1%
> 
> A combined 45.7% of the total market, which accounts for $7.13 billion.
> 
> 
> Conclusion:
> 
> So, if you are wondering if you should learn verilog or VHDL, the
> figures really say you should know both.  Well.  Really well.

.. and learn Quartus, as Altera's growth is well above Xilinx's ? :)

  Indeed, Xilinx's growth seems to be well below the average of the top 
5 in this sector ?

  In one table above, you have Altera as appx 2x Xilinx growth, but
in another shows ~3x - is that because the first table
excludes their hardcopy ASICs ?

  The second table also shows a larger Altera (lower ratio 
Xilinx:Altera) so something extra seems to be included here, that is 
missing in
what you call PLDs alone ?

-jg