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Xilinx IP wizard help

Started by Joseph May 26, 2006
I have a design from ISE that I have been trying to create a peripheral
out of.  I have created peripherals before using the wizard, but all
the logic was directly implemented in the user_logic.v stub that is
provided.  This time I have a few files that comprise my design and
don't want to/can't implement everything in user_logic.v.  I was able
to use the ISE project that is created with the peripheral (via the
wizard) to implement my design.  Essentially brought copies of my
already completed .v files to this new project and instantiated what I
needed into user_logic.v.  I was then able to successfully synthesize
the design in that ISE project.  Now when I try and use that IP in a
system in XPS, synthesis fails because the module I instantiate in
user_logic.v can't be found.  I have looked for documentation on how to
do this properly, but everything I have seen assumes everything the
user adds is contained completely in user_logic.v.  I have looked at
all the .prj files and tried to manipulate those with no
luck--synthesis fails the same way each time.  Am I missing something
obvious?  Has anyone done what I am describing?  Any pointers to
documentation on this?  I can provide more info if it helps...

Any help/advice appreciated,
Thanks,
Joey

Hi Joseph,

Look in:

peripheral repository/my_peripheral/data/my_peripheral.mpd
for I/O peripheral declaration

and in

peripheral repository/my_peripheral/data/my_peripheral.pao
for correct file linking (that's what you are probably looking for)

Have fun,

Guru

You should about the PAO syntax. This defines the set of files used for 
synthesis in the EDK world.

It's just point of organizing your files in the EDK directory structure 
and using the PAO to list the files in use.

Joseph wrote:
> I have a design from ISE that I have been trying to create a peripheral > out of. I have created peripherals before using the wizard, but all > the logic was directly implemented in the user_logic.v stub that is > provided. This time I have a few files that comprise my design and > don't want to/can't implement everything in user_logic.v. I was able > to use the ISE project that is created with the peripheral (via the > wizard) to implement my design. Essentially brought copies of my > already completed .v files to this new project and instantiated what I > needed into user_logic.v. I was then able to successfully synthesize > the design in that ISE project. Now when I try and use that IP in a > system in XPS, synthesis fails because the module I instantiate in > user_logic.v can't be found. I have looked for documentation on how to > do this properly, but everything I have seen assumes everything the > user adds is contained completely in user_logic.v. I have looked at > all the .prj files and tried to manipulate those with no > luck--synthesis fails the same way each time. Am I missing something > obvious? Has anyone done what I am describing? Any pointers to > documentation on this? I can provide more info if it helps... > > Any help/advice appreciated, > Thanks, > Joey >
Thanks for the quick response, Guru.  That .pao was what I needed.
Synthesis gets further now and it moved me to a new error that I was
sort of expecting.  In my design I am using a coregen module (a block
ram).  What do I need to include (and where)?  To get the IP design to
synthesize before (in the provided ISE project template), all I did was
add the .xco file I had to the new project and that was enough to get
things to work.  The .pao seems only for HDL files...

Thanks again for the help...
Joey

For presynthesized core components create pcores/data/my_peripheral.mdd
In this file specify which neltlists to include (must be in
pcores/netlist) for example:

Files

async_fifo.edn
clocker.ngc

Only EDN and NGC files are supported!

The last important thing: include in MPD the following line: OPTION
STYLE = MIX
to tell the XPS to search for DDB and netlists.

Have fun,

Guru