Newbie to FPGA

Hi,

I am a pre-si verification engineer looking to learn HW design,
synthesis and P&R through FPGAs.  (I am already very comfortable with
Verilog, so that is not the issue, I really want to learn to
"design+synthesize+P&R" as opposed to "code in verilog").

Recently checked out Spartan dev kit, looks very affordable.
Questions:

Is this the best way to go (for a hobbyist)? I am willing to spend
couple 100 $$ on dev kits etc. Ive already downloaded the ISE Webpack
and have full access to Modelsim at work.

What books should I get for DESIGN & SYNTHESIS (again, not verilog
coding but "designing" synthesizable code with Verilog). Please suggest
books with and without an FPGA "tilt" or focus if possible.


Once you do everything and download stuff into the FPGA, how do you run
the application?
For ex, if you design a H.264 encoder (just for example), and the FPGA
already has the code downloaded after Synthesis and P&R stage, how can
I pass an example stimulus file (ie H.264 stream) to see if it works
correctly?


My grand vision is to build a H.264 encoder module in an FPGA, while
teaching myself good design AND H.264 encoding in the process.


Am I missing anything here? Anything else I should know? 

Thanks

Just to add, I am already comfortable with poking around RTL and large
designs, I just havent done the design myself. (Victim of working in a
big company :-) )

Are there any more project ideas that will add value to my resume (such
as MPEG encoder/decoder etc) that I can do with an FPGA and check out
at home using a PC?
I have already started designing small modules (fifos etc, mostly
synchrounous).
Just getting into async fifo design, I still havent understood it
fully.

-Anand

anand wrote:
> Hi,
>
> I am a pre-si verification engineer looking to learn HW design,
> synthesis and P&R through FPGAs.  (I am already very comfortable with
> Verilog, so that is not the issue, I really want to learn to
> "design+synthesize+P&R" as opposed to "code in verilog").
>
> Recently checked out Spartan dev kit, looks very affordable.
> Questions:
>
> Is this the best way to go (for a hobbyist)? I am willing to spend
> couple 100 $$ on dev kits etc. Ive already downloaded the ISE Webpack
> and have full access to Modelsim at work.
>
> What books should I get for DESIGN & SYNTHESIS (again, not verilog
> coding but "designing" synthesizable code with Verilog). Please suggest
> books with and without an FPGA "tilt" or focus if possible.
>
>
> Once you do everything and download stuff into the FPGA, how do you run
> the application?
> For ex, if you design a H.264 encoder (just for example), and the FPGA
> already has the code downloaded after Synthesis and P&R stage, how can
> I pass an example stimulus file (ie H.264 stream) to see if it works
> correctly?
>
>
> My grand vision is to build a H.264 encoder module in an FPGA, while
> teaching myself good design AND H.264 encoding in the process.
>
>
> Am I missing anything here? Anything else I should know? 
> 
> Thanks

anand wrote:
> Just getting into async fifo design, I still havent understood it
> fully.
>
Using a dual-ported RAM, most of any asynchronous FIFO design is
trivial.
But the devil is in the flags (FULL and EMPTY) which get de-activated
by the "wrong" clock.
For example: EMPTY is activated by the read clock, and of importance
only in that read clock domain, but it gets de-activated by a write
clock. There is no defined phase relationship between the two clocks.
:-(
That clock-domain crossing requires Grray-coded address counters and
some trickery to avoid (or mitigate) metastability.

Just google, and read some papers by sunburst or Xilinx/yours truly,
like XAPP051.

Peter Alfke, Xilinx

Thanks Peter, I just downloaded XAPP051,

Can you (or someone else) provide some inputs on my post #1 above?
Thanks in advance.

-Anand
Peter Alfke wrote:
> anand wrote:
> > Just getting into async fifo design, I still havent understood it
> > fully.
> >
> Using a dual-ported RAM, most of any asynchronous FIFO design is
> trivial.
> But the devil is in the flags (FULL and EMPTY) which get de-activated
> by the "wrong" clock.
> For example: EMPTY is activated by the read clock, and of importance
> only in that read clock domain, but it gets de-activated by a write
> clock. There is no defined phase relationship between the two clocks.
> :-(
> That clock-domain crossing requires Grray-coded address counters and
> some trickery to avoid (or mitigate) metastability.
>
> Just google, and read some papers by sunburst or Xilinx/yours truly,
> like XAPP051.
> 
> Peter Alfke, Xilinx

The FPGA allows you to define the internal logic of a chip. After you
complete the logic design and simulation, you pass it through the
(Xilinx) place and route tool, which generates a bitstream of a few
million bits.
You feed this bitstream (in bit-serial or byte-parallel form) into the
FPGA (various methods, all well-described), and then you have your
custom chip, as long as you keep its Vcc up !
To make it do something, you feed its inputs and observe its outputs,
just as you would with a specialized custom chip, ASIC, memory,
microprocessor etc...

Was that too simplistic?
Peter Alfke
==================
anand wrote:
> Thanks Peter, I just downloaded XAPP051,
>
> Can you (or someone else) provide some inputs on my post #1 above?
> Thanks in advance.
>
> -Anand
> Peter Alfke wrote:
> > anand wrote:
> > > Just getting into async fifo design, I still havent understood it
> > > fully.
> > >
> > Using a dual-ported RAM, most of any asynchronous FIFO design is
> > trivial.
> > But the devil is in the flags (FULL and EMPTY) which get de-activated
> > by the "wrong" clock.
> > For example: EMPTY is activated by the read clock, and of importance
> > only in that read clock domain, but it gets de-activated by a write
> > clock. There is no defined phase relationship between the two clocks.
> > :-(
> > That clock-domain crossing requires Grray-coded address counters and
> > some trickery to avoid (or mitigate) metastability.
> >
> > Just google, and read some papers by sunburst or Xilinx/yours truly,
> > like XAPP051.
> > 
> > Peter Alfke, Xilinx

anand wrote:

> Hi,
> 
> I am a pre-si verification engineer looking to learn HW design,
> synthesis and P&R through FPGAs.  (I am already very comfortable with
> Verilog, so that is not the issue, I really want to learn to
> "design+synthesize+P&R" as opposed to "code in verilog").
> 
> Recently checked out Spartan dev kit, looks very affordable.
> Questions:
> 
> Is this the best way to go (for a hobbyist)? I am willing to spend
> couple 100 $$ on dev kits etc. Ive already downloaded the ISE Webpack
> and have full access to Modelsim at work.

Probably as good as any.
> 
> What books should I get for DESIGN & SYNTHESIS (again, not verilog
> coding but "designing" synthesizable code with Verilog). Please suggest
> books with and without an FPGA "tilt" or focus if possible.
> 
I use Thomas & Moorby's "The Verilog Hardware Description Language", 
which is mostly about Verilog but sprinkles in guidance for 
synthesizable designs.
> 
> Once you do everything and download stuff into the FPGA, how do you run
> the application?

You don't.  What's in an FPGA isn't an "application" and it doesn't 
"run" in the sense that an application does.  Once you've _configured_ 
the FPGA you let it loose, and off it goes doing whatever you coded it 
to do.

> For ex, if you design a H.264 encoder (just for example), and the FPGA
> already has the code downloaded after Synthesis and P&R stage, how can
> I pass an example stimulus file (ie H.264 stream) to see if it works
> correctly?
> 
You wouldn't really run a stimulus file through it -- you'd need to use 
(or generate) an appropriate stream to run in real life to wiggle the 
inputs pins on your FPGA.
> 
> My grand vision is to build a H.264 encoder module in an FPGA, while
> teaching myself good design AND H.264 encoding in the process.
> 
> 
> Am I missing anything here? Anything else I should know? 
> 
> Thanks
> 
You might want to start out a bit simpler -- I'd suggest blinking the 
lights, then maybe blinking the lights under the control of the switches.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html

>You wouldn't really run a stimulus file through it -- you'd need to use
>(or generate) an appropriate stream to run in real life to wiggle the
>inputs pins on your FPGA.

Thanks Tim. So, if I had to test the application in real life, then I
have to stimulate the input pins, correct? So, how do I go about
testing on the FPGA as to whether the design actually works in real
life (not in simulation)?  Assume I have a H.264 stream that I can use.

So in the dev board kit they have flash memory, I guess I can probably
load the flash memory with the stimulus stream. But question is, how do
I make it wiggle the appropriate pins of the FPGA itself, and how do I
collect the output to verify it?



Tim Wescott wrote:
> anand wrote:
>
> > Hi,
> >
> > I am a pre-si verification engineer looking to learn HW design,
> > synthesis and P&R through FPGAs.  (I am already very comfortable with
> > Verilog, so that is not the issue, I really want to learn to
> > "design+synthesize+P&R" as opposed to "code in verilog").
> >
> > Recently checked out Spartan dev kit, looks very affordable.
> > Questions:
> >
> > Is this the best way to go (for a hobbyist)? I am willing to spend
> > couple 100 $$ on dev kits etc. Ive already downloaded the ISE Webpack
> > and have full access to Modelsim at work.
>
> Probably as good as any.
> >
> > What books should I get for DESIGN & SYNTHESIS (again, not verilog
> > coding but "designing" synthesizable code with Verilog). Please suggest
> > books with and without an FPGA "tilt" or focus if possible.
> >
> I use Thomas & Moorby's "The Verilog Hardware Description Language",
> which is mostly about Verilog but sprinkles in guidance for
> synthesizable designs.
> >
> > Once you do everything and download stuff into the FPGA, how do you run
> > the application?
>
> You don't.  What's in an FPGA isn't an "application" and it doesn't
> "run" in the sense that an application does.  Once you've _configured_
> the FPGA you let it loose, and off it goes doing whatever you coded it
> to do.
>
> > For ex, if you design a H.264 encoder (just for example), and the FPGA
> > already has the code downloaded after Synthesis and P&R stage, how can
> > I pass an example stimulus file (ie H.264 stream) to see if it works
> > correctly?
> >
> You wouldn't really run a stimulus file through it -- you'd need to use
> (or generate) an appropriate stream to run in real life to wiggle the
> inputs pins on your FPGA.
> >
> > My grand vision is to build a H.264 encoder module in an FPGA, while
> > teaching myself good design AND H.264 encoding in the process.
> >
> >
> > Am I missing anything here? Anything else I should know?
> >
> > Thanks
> >
> You might want to start out a bit simpler -- I'd suggest blinking the
> lights, then maybe blinking the lights under the control of the switches.
>
> --
>
> Tim Wescott
> Wescott Design Services
> http://www.wescottdesign.com
>
> Posting from Google?  See http://cfaj.freeshell.org/google/
>
> "Applied Control Theory for Embedded Systems" came out in April.
> See details at http://www.wescottdesign.com/actfes/actfes.html

One of the things you can do is to build a stimulus mechanism into your 
design for both early testing both for simulation and for running in the 
real chip. Just remember to write it to be synthesisable not testbench 
style. Once you are confident it is probably working introduce your real 
source and sort out any issues caused by it being different to your internal 
stimulus mechanism. For instance dealing with real setup and hold on input 
signals.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


"anand" <writeanand@gmail.com> wrote in message 
news:1150684323.749607.70170@c74g2000cwc.googlegroups.com...
> >You wouldn't really run a stimulus file through it -- you'd need to use
>>(or generate) an appropriate stream to run in real life to wiggle the
>>inputs pins on your FPGA.
>
> Thanks Tim. So, if I had to test the application in real life, then I
> have to stimulate the input pins, correct? So, how do I go about
> testing on the FPGA as to whether the design actually works in real
> life (not in simulation)?  Assume I have a H.264 stream that I can use.
>
> So in the dev board kit they have flash memory, I guess I can probably
> load the flash memory with the stimulus stream. But question is, how do
> I make it wiggle the appropriate pins of the FPGA itself, and how do I
> collect the output to verify it?
>
>
>
> Tim Wescott wrote:
>> anand wrote:
>>
>> > Hi,
>> >
>> > I am a pre-si verification engineer looking to learn HW design,
>> > synthesis and P&R through FPGAs.  (I am already very comfortable with
>> > Verilog, so that is not the issue, I really want to learn to
>> > "design+synthesize+P&R" as opposed to "code in verilog").
>> >
>> > Recently checked out Spartan dev kit, looks very affordable.
>> > Questions:
>> >
>> > Is this the best way to go (for a hobbyist)? I am willing to spend
>> > couple 100 $$ on dev kits etc. Ive already downloaded the ISE Webpack
>> > and have full access to Modelsim at work.
>>
>> Probably as good as any.
>> >
>> > What books should I get for DESIGN & SYNTHESIS (again, not verilog
>> > coding but "designing" synthesizable code with Verilog). Please suggest
>> > books with and without an FPGA "tilt" or focus if possible.
>> >
>> I use Thomas & Moorby's "The Verilog Hardware Description Language",
>> which is mostly about Verilog but sprinkles in guidance for
>> synthesizable designs.
>> >
>> > Once you do everything and download stuff into the FPGA, how do you run
>> > the application?
>>
>> You don't.  What's in an FPGA isn't an "application" and it doesn't
>> "run" in the sense that an application does.  Once you've _configured_
>> the FPGA you let it loose, and off it goes doing whatever you coded it
>> to do.
>>
>> > For ex, if you design a H.264 encoder (just for example), and the FPGA
>> > already has the code downloaded after Synthesis and P&R stage, how can
>> > I pass an example stimulus file (ie H.264 stream) to see if it works
>> > correctly?
>> >
>> You wouldn't really run a stimulus file through it -- you'd need to use
>> (or generate) an appropriate stream to run in real life to wiggle the
>> inputs pins on your FPGA.
>> >
>> > My grand vision is to build a H.264 encoder module in an FPGA, while
>> > teaching myself good design AND H.264 encoding in the process.
>> >
>> >
>> > Am I missing anything here? Anything else I should know?
>> >
>> > Thanks
>> >
>> You might want to start out a bit simpler -- I'd suggest blinking the
>> lights, then maybe blinking the lights under the control of the switches.
>>
>> --
>>
>> Tim Wescott
>> Wescott Design Services
>> http://www.wescottdesign.com
>>
>> Posting from Google?  See http://cfaj.freeshell.org/google/
>>
>> "Applied Control Theory for Embedded Systems" came out in April.
>> See details at http://www.wescottdesign.com/actfes/actfes.html
> 

How about a freely available PicoBlaze microcontroller? I assume you
can probably write assembly code for the PicoBlaze and that in turn
drives the stimulus to the chip.

As for the collection/monitoring of outputs, I believe the Picoblaze
can read from the FPGA output pins and either do print statements or
populate its own registers for offline reading.

Would this work?


John Adair wrote:
> One of the things you can do is to build a stimulus mechanism into your
> design for both early testing both for simulation and for running in the
> real chip. Just remember to write it to be synthesisable not testbench
> style. Once you are confident it is probably working introduce your real
> source and sort out any issues caused by it being different to your internal
> stimulus mechanism. For instance dealing with real setup and hold on input
> signals.
>
> John Adair
> Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development
> Board.
> http://www.enterpoint.co.uk
>
>
> "anand" <writeanand@gmail.com> wrote in message
> news:1150684323.749607.70170@c74g2000cwc.googlegroups.com...
> > >You wouldn't really run a stimulus file through it -- you'd need to use
> >>(or generate) an appropriate stream to run in real life to wiggle the
> >>inputs pins on your FPGA.
> >
> > Thanks Tim. So, if I had to test the application in real life, then I
> > have to stimulate the input pins, correct? So, how do I go about
> > testing on the FPGA as to whether the design actually works in real
> > life (not in simulation)?  Assume I have a H.264 stream that I can use.
> >
> > So in the dev board kit they have flash memory, I guess I can probably
> > load the flash memory with the stimulus stream. But question is, how do
> > I make it wiggle the appropriate pins of the FPGA itself, and how do I
> > collect the output to verify it?
> >
> >
> >
> > Tim Wescott wrote:
> >> anand wrote:
> >>
> >> > Hi,
> >> >
> >> > I am a pre-si verification engineer looking to learn HW design,
> >> > synthesis and P&R through FPGAs.  (I am already very comfortable with
> >> > Verilog, so that is not the issue, I really want to learn to
> >> > "design+synthesize+P&R" as opposed to "code in verilog").
> >> >
> >> > Recently checked out Spartan dev kit, looks very affordable.
> >> > Questions:
> >> >
> >> > Is this the best way to go (for a hobbyist)? I am willing to spend
> >> > couple 100 $$ on dev kits etc. Ive already downloaded the ISE Webpack
> >> > and have full access to Modelsim at work.
> >>
> >> Probably as good as any.
> >> >
> >> > What books should I get for DESIGN & SYNTHESIS (again, not verilog
> >> > coding but "designing" synthesizable code with Verilog). Please suggest
> >> > books with and without an FPGA "tilt" or focus if possible.
> >> >
> >> I use Thomas & Moorby's "The Verilog Hardware Description Language",
> >> which is mostly about Verilog but sprinkles in guidance for
> >> synthesizable designs.
> >> >
> >> > Once you do everything and download stuff into the FPGA, how do you run
> >> > the application?
> >>
> >> You don't.  What's in an FPGA isn't an "application" and it doesn't
> >> "run" in the sense that an application does.  Once you've _configured_
> >> the FPGA you let it loose, and off it goes doing whatever you coded it
> >> to do.
> >>
> >> > For ex, if you design a H.264 encoder (just for example), and the FPGA
> >> > already has the code downloaded after Synthesis and P&R stage, how can
> >> > I pass an example stimulus file (ie H.264 stream) to see if it works
> >> > correctly?
> >> >
> >> You wouldn't really run a stimulus file through it -- you'd need to use
> >> (or generate) an appropriate stream to run in real life to wiggle the
> >> inputs pins on your FPGA.
> >> >
> >> > My grand vision is to build a H.264 encoder module in an FPGA, while
> >> > teaching myself good design AND H.264 encoding in the process.
> >> >
> >> >
> >> > Am I missing anything here? Anything else I should know?
> >> >
> >> > Thanks
> >> >
> >> You might want to start out a bit simpler -- I'd suggest blinking the
> >> lights, then maybe blinking the lights under the control of the switches.
> >>
> >> --
> >>
> >> Tim Wescott
> >> Wescott Design Services
> >> http://www.wescottdesign.com
> >>
> >> Posting from Google?  See http://cfaj.freeshell.org/google/
> >>
> >> "Applied Control Theory for Embedded Systems" came out in April.
> >> See details at http://www.wescottdesign.com/actfes/actfes.html
> >

How about a freely available PicoBlaze microcontroller? I assume you
can probably write assembly code for the PicoBlaze and that in turn
drives the stimulus to the chip.

As for the collection/monitoring of outputs, I believe the Picoblaze
can read from the FPGA output pins and either do print statements or
populate its own registers for offline reading.


Would this work?



John Adair wrote:
> One of the things you can do is to build a stimulus mechanism into your
> design for both early testing both for simulation and for running in the
> real chip. Just remember to write it to be synthesisable not testbench
> style. Once you are confident it is probably working introduce your real
> source and sort out any issues caused by it being different to your internal
> stimulus mechanism. For instance dealing with real setup and hold on input
> signals.
>
> John Adair
> Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development
> Board.
> http://www.enterpoint.co.uk
>
>
> "anand" <writeanand@gmail.com> wrote in message
> news:1150684323.749607.70170@c74g2000cwc.googlegroups.com...
> > >You wouldn't really run a stimulus file through it -- you'd need to use
> >>(or generate) an appropriate stream to run in real life to wiggle the
> >>inputs pins on your FPGA.
> >
> > Thanks Tim. So, if I had to test the application in real life, then I
> > have to stimulate the input pins, correct? So, how do I go about
> > testing on the FPGA as to whether the design actually works in real
> > life (not in simulation)?  Assume I have a H.264 stream that I can use.
> >
> > So in the dev board kit they have flash memory, I guess I can probably
> > load the flash memory with the stimulus stream. But question is, how do
> > I make it wiggle the appropriate pins of the FPGA itself, and how do I
> > collect the output to verify it?
> >
> >
> >
> > Tim Wescott wrote:
> >> anand wrote:
> >>
> >> > Hi,
> >> >
> >> > I am a pre-si verification engineer looking to learn HW design,
> >> > synthesis and P&R through FPGAs.  (I am already very comfortable with
> >> > Verilog, so that is not the issue, I really want to learn to
> >> > "design+synthesize+P&R" as opposed to "code in verilog").
> >> >
> >> > Recently checked out Spartan dev kit, looks very affordable.
> >> > Questions:
> >> >
> >> > Is this the best way to go (for a hobbyist)? I am willing to spend
> >> > couple 100 $$ on dev kits etc. Ive already downloaded the ISE Webpack
> >> > and have full access to Modelsim at work.
> >>
> >> Probably as good as any.
> >> >
> >> > What books should I get for DESIGN & SYNTHESIS (again, not verilog
> >> > coding but "designing" synthesizable code with Verilog). Please suggest
> >> > books with and without an FPGA "tilt" or focus if possible.
> >> >
> >> I use Thomas & Moorby's "The Verilog Hardware Description Language",
> >> which is mostly about Verilog but sprinkles in guidance for
> >> synthesizable designs.
> >> >
> >> > Once you do everything and download stuff into the FPGA, how do you run
> >> > the application?
> >>
> >> You don't.  What's in an FPGA isn't an "application" and it doesn't
> >> "run" in the sense that an application does.  Once you've _configured_
> >> the FPGA you let it loose, and off it goes doing whatever you coded it
> >> to do.
> >>
> >> > For ex, if you design a H.264 encoder (just for example), and the FPGA
> >> > already has the code downloaded after Synthesis and P&R stage, how can
> >> > I pass an example stimulus file (ie H.264 stream) to see if it works
> >> > correctly?
> >> >
> >> You wouldn't really run a stimulus file through it -- you'd need to use
> >> (or generate) an appropriate stream to run in real life to wiggle the
> >> inputs pins on your FPGA.
> >> >
> >> > My grand vision is to build a H.264 encoder module in an FPGA, while
> >> > teaching myself good design AND H.264 encoding in the process.
> >> >
> >> >
> >> > Am I missing anything here? Anything else I should know?
> >> >
> >> > Thanks
> >> >
> >> You might want to start out a bit simpler -- I'd suggest blinking the
> >> lights, then maybe blinking the lights under the control of the switches.
> >>
> >> --
> >>
> >> Tim Wescott
> >> Wescott Design Services
> >> http://www.wescottdesign.com
> >>
> >> Posting from Google?  See http://cfaj.freeshell.org/google/
> >>
> >> "Applied Control Theory for Embedded Systems" came out in April.
> >> See details at http://www.wescottdesign.com/actfes/actfes.html
> >