RS232 to access TX registers of Aurora

New problem:
When I send the 8-bit test data like for eg.X"31", it should appear on
the screen as "01".However this is not taking place. The terminal has
baud rate 19200, 8 data bits, 1 stop bit and no flow control.
what do I have to specify as start and stop bits?? Moreover I am using
the files obtained from Heron Engg...IF anyone has worked on this,
lemme know.
Thanks,
Vivek


Vivek Menon wrote:
> Thanks Duane.
> I have 16-bit data that needs to be converted to ASCII.
> SO I guess I will have to take a nibble and convert it into its ASCII
> equivalent and then give a space or next line to differentiate the next
> word.
> Thanks for the tip.
> Vivek
> Duane Clark wrote:
> > Vivek Menon wrote:
> > > does anybody have a function or package that converts data into ASCII??
> >
> > You send one nibble (4 bits) at a time. If the nibble is between 0-9,
> > then add 0x30 (hex 30). If between a-f, add 0x60. It should be easy to
> > figure out how to do that in VHDL/Verilog. That will give you a hex display.

Vivek Menon wrote:
> New problem:
> When I send the 8-bit test data like for eg.X"31", it should appear on
> the screen as "01".However this is not taking place. The terminal has
> baud rate 19200, 8 data bits, 1 stop bit and no flow control.
> what do I have to specify as start and stop bits?? Moreover I am using
> the files obtained from Heron Engg...IF anyone has worked on this,

I don't know what Heron Engg is. But X"31" will display as "1" not "01".

Have you simulated it and seen what the output looks like? The output 
should be high when not sending data, there is a single bit '0' as the 
start bit, then the 8 bits of data LSB first, then a '1' stop bit. That 
can be immediately followed by another start bit if more data is ready 
to be sent, else the output remains at '1' until more data is ready to 
be sent. Each bit should be 1/19200 seconds or approximately 52uS, but 
that does not need to be exact; a few percent difference is tolerable.

There should be an RS232 interface chip between the FPGA and your serial 
cable.

Hi Duane,
Instead of the Heron Eng, I used tha xapp341.pdf file from Xilinx that
describes an implementation of a RS232 transmitter and receiver. I used
only the transmitter. The testbench simulates properly on Modelsim.
Now I used a baud generator suggested in this grp by Peter Hermannson
to divide the 100 MHz clock  by 325.5  to get 19200 baud rate and
provided it to the clk of the RS232 transmitter. This module has a
strobe signal. I assigned a push button to it and inverted the logic
levels so that it works similar to the test bench.
Still I don't see anything on the terminal..Any pointers??
Thanks,
Vivek
Duane Clark wrote:
> Vivek Menon wrote:
> > New problem:
> > When I send the 8-bit test data like for eg.X"31", it should appear on
> > the screen as "01".However this is not taking place. The terminal has
> > baud rate 19200, 8 data bits, 1 stop bit and no flow control.
> > what do I have to specify as start and stop bits?? Moreover I am using
> > the files obtained from Heron Engg...IF anyone has worked on this,
>
> I don't know what Heron Engg is. But X"31" will display as "1" not "01".
>
> Have you simulated it and seen what the output looks like? The output
> should be high when not sending data, there is a single bit '0' as the
> start bit, then the 8 bits of data LSB first, then a '1' stop bit. That
> can be immediately followed by another start bit if more data is ready
> to be sent, else the output remains at '1' until more data is ready to
> be sent. Each bit should be 1/19200 seconds or approximately 52uS, but
> that does not need to be exact; a few percent difference is tolerable.
>
> There should be an RS232 interface chip between the FPGA and your serial
> cable.

Hi
I am using Ken Chapman's UART cores described in xapp223.pdf from
Xilinx. I am having mapping errors.
Has anyone worked on this??
Thanks,
Vivek