verilog versus vhdl

On Tue, 08 Aug 2006 07:04:10 -0700,
Ron <News5@spamex.com> wrote:

>How about:

urrm, does the smiley apply to the whole post ? 

>1. if/else are the same.

C has a hard time with "if (1'bx)".

>2. Verilog "begin" and "end" maps to C's "{" and "}"

I'll grant you that one.

>3. Verilog's case statement is similar to C's switch statement.

Apart from the facts that:
* each branch is a single statement in Verilog,
  whereas C switch is in fact a computed branch and 
  execution continues through the switch block;
* choices must be prefixed with the keyword "case" in C;
* the syntax for mapping more than one choice
  to the same action is different;
* Verilog has two wildcard-matching variants of "case";
* case labels (choices) in Verilog don't need to be constants.

In other respects, yes, they're similar....

>4. Comment characters are the same.
>5. Verilog and C statements are both terminated with semicolon.

OK, I concede.

>6. And last but not least, both Verilog and C have "integer" types. ;-)

with different names and different semantics :-)
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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are not the views of Doulos Ltd., unless specifically stated.

Ben Jones wrote:
> "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
> Still, I'd rather type '&' than 'and' anyday. :)

Personally, I'd rather read 'and' than '&'.  The old Ada argument is 
that code is read far more often than it is written.  I guess that's why 
Ada-inspired VHDL ended up as it did.  IMHO the world needs both, 
Verilog for hacking together things at low-level very quickly and 
easily, VHDL for larger projects, particularly those being written by a 
large team.  There's also plenty of room for personal preference of 
course...

-- Peter

Evan Lavelle wrote:
> Personally, I really hate this sort of code. It was synthesising to
> about 75 logic levels between clocks before I started hacking it.

I will agree that bad synthesis prevent abstract use, and that given
enough time a human can normally find a better solution. On the
otherhand, large designs, and fixed market windows, force tradeoffs.
And as the complexity of designs grow to take advantage of FPGAs which
grow in size with Moore's Law, we probably are not going to see either
the number of skilled FPGA hackers (err hardware designers) salary
shrink to maintain the same costs or see market windows increasing in
length with Moore's Law. So that says, the tools must improve, as must
the coding efficiency of hardware hackers.

> >I'm actually looking foward to a SystemC tool based
> >on C++ sematics that has really good synthesis ... maybe a few years
> >from now?
>
> It'll never happen; already been tried, failed. Hacking low-level
> hardware semantics into existing C++ semantics just gives you a
> verbose and complex mess, which is nowhere near as concise and clear
> as a VHDL or Verilog description. Great for modelling, non-starter for
> real-world synthesis.

I love people quoting other failures as proof of impossibiity.

I'm sure the experience set in this forum is rife with examples of
designs that "would never happen", because a few teams failed, and over
time other people learn new skills, tricks, tools and find the
solutions to previously difficult problems. It wasn't that long ago
that the DEC systems engineers defended writing in assembly long after
the industry moved past that poor practice. Of course, the industry
moved past DEC too.  And a couple of my "favorite" hardware companies
that swore large TTL design where cheaper, that have long since bit the
dust too.

> BTW, I google'd FpgaC and spent 10 minutes looking at the SourceForge
> site, before giving up. There's no obvious overview, FAQ, or
> documentation; you'll need to fix this if you want to get anyone
> interested.

it's not prime time yet, still has about two more major changes to be
release as Beta's this year. There hasn't been a need yet for an FAQ,
but everything else in your list is in the Source Forge archive in all
the expected spots.

http://sourceforge.net/docman/display_doc.php?docid=30867&group_id=152034
http://fpgac.sourceforge.net/

and the current development snapshot gets checked into the publicly
accessable svn archive as changes are integrated into the main
development tree, including doc updates. I have my own development tree
of major hacks and work in progress ideas, that get pushed up to the
svn archive as they are nearing a point in development that they ready
for others to play with.

As a work in progress, it's certainly far from complete today, and
probaby would have been a lot farther complete, except for the drowning
death of my 11 year old daughter at a friends house in May. As close as
I can tell, there are a good few using it, from the periodic emails.
Mostly students that are comfortable with the work in progress state of
the project, and are willing to spend a small amount of time to hack
the tools into a working state for their development environment.

Clean, plug and play release which are married well to Altera and
Xilinx tools, will probably not happen till Beta-4 around Christmas. At
which point FpgaC will go pretty close to production, with some
maturity and ease of use work.

On Tue, 08 Aug 2006 12:26:05 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

>> In summary: &&, ||, !, &, |, ^, ~, ==, !=. :-)
>
>And even that is at the mercy of 4-state logic.

Even for these operators, the usage semantics (as you know) are very
different from C's. Sections 4.4/4.5 of the LRM are fantastically
complicated (to me, anyway). To quote Steven Sharp from an old c.l.v
post on the subject: "I agree that this is not intuitive to someone
used to most other programming languages". Too right.

>(I spy a missed opportunity here.  SystemVerilog has not yet 
>assigned a meaning to the :-) operator.)

Damn... I was going to say that :-)

On Tue, 8 Aug 2006 15:26:05 +0100, "Ben Jones" <ben.jones@xilinx.com>
wrote:

>
>"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
>news:gcsgd254tgh90tmsdq5pkg2fgl3vmj3bu8@4ax.com...
>> On Tue, 8 Aug 2006 11:04:38 +0100, Ben Jones
>>  <ben.jones@xilinx.com> wrote:
>
>> > In summary: &&, ||, !, &, |, ^, ~, ==, !=. :-)
>> And even that is at the mercy of 4-state logic.
>
>Still, I'd rather type '&' than 'and' anyday. :)

That reminds me. C++ has 'and', 'or', 'xor', and 'not' operators. Now,
this could just be a bizarre coincidence, but I think not. A more
reasonable explanation, I contend, is that Mr. Stroustrup actually
based C++ on VHDL.

Evan

Jonathan Bromley wrote:
> urrm, does the smiley apply to the whole post ?

Certainly not ... as one expression per post can be horribly boring :(

> C has a hard time with "if (1'bx)".

Ummm ... Why is that construct difficult for C?

> Apart from the facts that:
> * each branch is a single statement in Verilog,
>   whereas C switch is in fact a computed branch and
>   execution continues through the switch block;

Something that makes switch statements "interesting" for FpgaC at the
moment because of the current "one-hot" notion about flow control. That
abstraction however, isn't pure, and will certainly get less pure soon,
when switch/case/break/continue are implemented using a mapped set of
enables (rather than a pure mux tree).

> In other respects, yes, they're similar....

Historically, in the evolution of languages, C defined a number of
departures in syntax that have been adopted in new languages rather
than the more verbose 1970's styles found in Pascal, ADA, PL/1
predicessors.

Evan Lavelle wrote:

>  A more
> reasonable explanation, I contend, is that Mr. Stroustrup actually
> based C++ on VHDL.

Hmm ... C++ was presented initially released as part of the programmers
workbench sometime in the spring of 1975 if I remember right. Verilog
was a decade later in 1985. When was VHDL?

fpga_toys@yahoo.com wrote:
> Evan Lavelle wrote:
>
> >  A more
> > reasonable explanation, I contend, is that Mr. Stroustrup actually
> > based C++ on VHDL.
>
> Hmm ... C++ was presented initially released as part of the programmers
> workbench sometime in the spring of 1975 if I remember right. Verilog
> was a decade later in 1985. When was VHDL?

hmm ... so much for memory ... googling seems place it early 1980's too.

On Tue, 08 Aug 2006 16:59:59 +0100,
Evan Lavelle <eml@nospam.uk> wrote:

>Even for these 
[bitwise logic]
>operators, the usage semantics (as you know) are very
>different from C's. Sections 4.4/4.5 of the LRM are fantastically
>complicated (to me, anyway). To quote Steven Sharp from an old c.l.v
>post on the subject: "I agree that this is not intuitive to someone
>used to most other programming languages". Too right.

We must be grateful for small mercies.  At least it's written down
in the LRM now.  Until V-2001, the only place to go for real
understanding of Verilog's bit width rules was Steven Sharp's
consistently informative and precise postings on c.l.v.

And don't even ask about short-circuit evaluation of 
boolean expressions... another non-similarity between
C and Verilog.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On 8 Aug 2006 09:24:56 -0700, fpga_toys@yahoo.com wrote:

>hmm ... so much for memory ... googling seems place it 
[C++]
>early 1980's too.

I had understood that Stroustrup was working on "C with Classes"
(using a preprocessor to map from CwC to pure C) from around 1978.
Methinks Evan was being whimsical about VHDL...
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.