verilog versus vhdl

"Markus Zingg" <m.zingg@nct.ch> wrote in message
news:vdj9d2hnlfdprab5q048vv0si9qiplrnf6@4ax.com...
> Hi Group
>
> I have to implement a design which requires an FPGA, but to do so
> among other things I obviousely first have to learn one of the two
> mentioned languages.

Doesn't seem that obvious to me... learn both! Your life will then be much
easier. :-)

For my part, I prefer the "look" of Verilog but the "feel" of VHDL, if that
makes sense. Both languages have good points and bad points, but on the
whole I like VHDL best. I'd say it has a longer learning curve than Verilog,
but once you've got to the top of it the view is much nicer.

Cheers,

        -Ben-

Markus Zingg <m.zingg@nct.ch> writes:

> Hi Group
> 
> I have to implement a design which requires an FPGA, but to do so
> among other things I obviousely first have to learn one of the two
> mentioned languages. I got the impression that europe seems to be more
> vhdl centric whereas verilog seems to be more popular in the US but
> this argument alone is for reasons beond the scope of this question
> not so important to me. I have a strong background in C programming
> (should that matter anyhow) and in general experience with embedded
> systems, but FPGAs are new to me. I'm otherwise completely open and
> alas wonder what you guys suggest I should choose. I'm mostly
> interested in replies from people which know both languages cause
> otherwise I fear that this thread ends up in some sort of religious
> war...
> 

I've seen this description on comp.lang.vhdl:
http://groups.google.co.uk/group/comp.lang.vhdl/browse_thread/thread/ecda44d121d1905c/a1df8e111cd1fbd7?lnk=st&q=&rnum=1&hl=en#a1df8e111cd1fbd7

"Verilog was designed by a bunch of hardware guys who didn't know a
thing about designing software. We had to beat on it before we could
make any real work with it.

VHDL was designed by a bunch of software guys who didn't know a thing
about designing hardware. We had to beat on it before we could make
any real work with it."

Not that it helps you any!

Personally, I prefer VHDL because the strong-typing means the compiler
can catch lots of problems for you.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt  
   

On Sat, 05 Aug 2006 19:02:31 +0200, Markus Zingg wrote:

> Hi Group
> 
> I have to implement a design which requires an FPGA, but to do so
> among other things I obviousely first have to learn one of the two
> mentioned languages. I got the impression that europe seems to be more
> vhdl centric whereas verilog seems to be more popular in the US but
> this argument alone is for reasons beond the scope of this question
> not so important to me. I have a strong background in C programming
> (should that matter anyhow) and in general experience with embedded
> systems, but FPGAs are new to me. I'm otherwise completely open and
> alas wonder what you guys suggest I should choose. I'm mostly
> interested in replies from people which know both languages cause
> otherwise I fear that this thread ends up in some sort of religious
> war...
> 
> TIA
> 
> Markus

I strongly prefer Verilog. It's C like which makes it much easier to read
for a C programmer. It's very concise which also makes it easier to read
and write. Like C it's easy to write very efficient code with Verilog. On
the downside it's missing a lot of C's important features like structures
and procedures. Verilog has simple functions and a weak task mechanism
instead of C's procedures. However I haven't found that limiting. 

VHDL is a much more complex language than Verilog. VHDL code is very
verbose, painfully so. However it does have capabilities that Verilog
doesn't have. Where Verilog errs on the side of being to simple, VHDL errs
on the side of being to complex.

Josh Rosen wrote:
> On Sat, 05 Aug 2006 19:02:31 +0200, Markus Zingg wrote:
>
> > Hi Group
> >
> > I have to implement a design which requires an FPGA, but to do so
> > among other things I obviousely first have to learn one of the two
> > mentioned languages. I got the impression that europe seems to be more
> > vhdl centric whereas verilog seems to be more popular in the US but
> > this argument alone is for reasons beond the scope of this question
> > not so important to me. I have a strong background in C programming
> > (should that matter anyhow) and in general experience with embedded
> > systems, but FPGAs are new to me. I'm otherwise completely open and
> > alas wonder what you guys suggest I should choose. I'm mostly
> > interested in replies from people which know both languages cause
> > otherwise I fear that this thread ends up in some sort of religious
> > war...
> >
> > TIA
> >
> > Markus
>
> I strongly prefer Verilog. It's C like which makes it much easier to read
> for a C programmer. It's very concise which also makes it easier to read
> and write. Like C it's easy to write very efficient code with Verilog. On
> the downside it's missing a lot of C's important features like structures
> and procedures. Verilog has simple functions and a weak task mechanism
> instead of C's procedures. However I haven't found that limiting.
>
> VHDL is a much more complex language than Verilog. VHDL code is very
> verbose, painfully so. However it does have capabilities that Verilog
> doesn't have. Where Verilog errs on the side of being to simple, VHDL errs
> on the side of being to complex.

First off, I learned VHDL because that is what my employer uses - which
I suspect most people end up doing. That said, I'm presently trying to
learn Verilog, in order to be more versatile. I was trained in digital
logic, so I found VHDL fairly trivial to learn. Verilog doesn't appear
to be all that difficult either. Note, I'm not talking about being an
expert in all of the nuances - I'm still learning those - I'm talking
about being able to get busy designing hardware.

Also, the verbosity of VHDL can be managed. A lot of the stuff people
complain about is optional. For example, you don't have to put the
process/architecture/package/etc. name at the end. You can just "end"
it. Same goes for a lot of other structures. You can also declare
subtypes and types that reduce a lot of typing, and make things more
clear.

Yes, you do need to be fairly intimate with the language to get to this
point, but once you do, you can describe hardware pretty darn quick.

I will admit, there are still things in VHDL that bug me. Semicolon
use, for example, almost seems arbitrary. I've gotten used to it, but I
still occasionally foul up with semicolons.

David R Brooks <davebXXX@iinet.net.au> wrote:

>It certainly is a religious war :-)
>FWIW, VHDL derives more from Ada, while Verilog derives from C.
>This means that VHDL is strongly typed, while (classic) Verilog is not. 
>That may be a plus or a minus, according to your viewpoint.

Heh, a hardware engineer once told me the only thing you need to remember
with VHDL is to only ever use one type.....

-- 

Markus Zingg wrote:


> I have to implement a design which requires an FPGA, but to do so
> among other things I obviousely first have to learn one of the two
> mentioned languages.

Take a book, that teaches both languages and learn that language, that 
your employer requires first. Learn the other language as you need it.

"HDL Chip Design" by Douglas Smith was the book I took.


> I have a strong background in C programming
> (should that matter anyhow) ...

Verilog looks like C. This can be an advantage while learning the syntax 
and a big disadvantage, because modeling hardware not is the same as 
writing software.


VHDL needs more characters to type (the code becomes bigger) but a lot 
of parts of the syntax is self-explaining. But because you have strong C 
background this is not so important.

VHDL is strongly typed. A lot of people complain, because that forces 
them to write want they want but on the other hand a lot of typing 
errors are trapped by the syntax check. Verilog is the opposite: Less to 
type, but with a lot of pitfalls for errors.
There is a award-winning paper by Clifford E. Cummings: "Nonblocking 
Assignments in Verilog Synthesis, Coding Styles That Kill!" A lot of 
pitfalls and none of them would have happened if VHDL would have been 
chosen.

I personally prefer VHDL but the boss and the costumer decide what I 
have to do.

Ralf

I can't remember who in this newsgroup who knows both and, whichever 
he's using at any given moment, always regrets he doesn't use the other 
language.

Nicolas

Prior to a few years ago, my design style would have been pretty much
applicable to either language with little impact, even though I use
vhdl.

However, in the last few years, I have started using variables instead
of signals in vhdl, the former being akin to blocking assignments in
verilog, but without the accompanying race-condition risks associated
with verilog.  The resulting descriptions are much more like SW, in
that when a variable is assigned, it is immediately updated, and
subsequent references to it are to the updated value.  With VHDL
signals, or Verilog non-blocking assignments (the most commonly used
kind), the code looks like SW, but does not read or execute like it
because of the magical postponement of the updates.

I now tend to use single, clocked processes within an architecture
(akin to a module in verilog), with variables for everything,
registered or combinatorial, except the IO. Granted, Verilog would also
work if I used the same style, but it is way too easy in Verilog to use
the wrong type of assignment when you are using both kinds, and there
are no protections against doing so.  In VHDL you cannot do a blocking
assignment to a signal, and you cannot do a non-blocking assignment to
a variable. Since a variable cannot be read by another process, there
is no chance of a race condition.

Both languages are completely capable of describing virtually any
digital logic system that is possible to build (and quite a few that
are not!), but it boils down to a particular style, and the pros and
cons of that style for a particular user, customer, or organization.

Andy

Hi,

All this information is very interesting. I didn't want to make a new
thread for my question but I was wondering which of these languages can
be used more error-freely while using Xilinx CAD tools ISE and EDK.
Because I already know some Verilog however thinking that VHDL is a
more widely used language!!, I didn't actually dare to use Verilog for
my designs to do simulation or other things that I had to deal with low
level HDL in the tools. I really prefer to use Verilog as I'm more
comfortable with it and I don't want to spend much time learning VHDL
at this time. But I'm afraid  that I have to deal with some errors in
EDK or ISE or in my simulation because Verilog is not strongly
supported by Xilinx tools. Do you have any idea about that?
Will I probably face problems just because I'm using Verilog.

Thanks,

Amir

Nicolas Matringe wrote:
> I can't remember who in this newsgroup who knows both and, whichever
> he's using at any given moment, always regrets he doesn't use the other
> language.
> 
> Nicolas

If your concern is how well Xilinx XST supports Verilog,
I'd have to say it's pretty good.  I've been using the
Xilinx tools with Verilog for a number of years now and
it works fine.

I'd say that picking VHDL or Verilog is not dependant
on the tool support.  The tools usually will work fine
with either language.  The choice should be made on
which language will work best for YOU, not based
on the Xilinx tools.

John Providenza

Xesium wrote:
> Hi,
>
> All this information is very interesting. I didn't want to make a new
> thread for my question but I was wondering which of these languages can
> be used more error-freely while using Xilinx CAD tools ISE and EDK.
> Because I already know some Verilog however thinking that VHDL is a
> more widely used language!!, I didn't actually dare to use Verilog for
> my designs to do simulation or other things that I had to deal with low
> level HDL in the tools. I really prefer to use Verilog as I'm more
> comfortable with it and I don't want to spend much time learning VHDL
> at this time. But I'm afraid  that I have to deal with some errors in
> EDK or ISE or in my simulation because Verilog is not strongly
> supported by Xilinx tools. Do you have any idea about that?
> Will I probably face problems just because I'm using Verilog.
>
> Thanks,
>
> Amir
>
> Nicolas Matringe wrote:
> > I can't remember who in this newsgroup who knows both and, whichever
> > he's using at any given moment, always regrets he doesn't use the other
> > language.
> > 
> > Nicolas