"Jeff Cunningham" <jcc@sover.net> wrote in message news:44d7f7d1$0$6591$4d3efbfe@news.sover.net...> ZHI wrote: >> Thanks Mike Treseler >> I am not reading a vhdl netlist. I am reading a uart application >> codes. For example, the input signal (RXD signal) of FPGA firstly >> go through a IBUF then a BUFG. What's the uses of them respectively? >> Why need use these buffers? When need use them? >> Or we actually don't need to care these buffers at all. > > BUFG is a buffer which drives a global clock network. > IBUF is a buffer from the input pin. > > IBUF->BUFG would typically be used when an external pin is used to drive a > clock signal and the pin is NOT a dedicated clock input. > > Ideally a synthesizer would handle this automatically. Sometimes the tool > is not smart enough. Instantiating BUFG directly forces it to route the > signal on a global clock net. >Sometimes the tool is too smart, and sometimes what you need cannot be properly inferred. In a multiple clock design, I prefer to direct which clocks get which bufg's. I may also want to direct the naming to facilitate placement control in the constraints file. There are many potential reasons for doing direct VHDL instantation of a specific component. Nevertheless, I have difficulty with the idea of explicity instantiating hundreds of IBUFs and OBUFs in my code. The tools have matured to the extent that those key pieces will be inferred and created in the edif netlist. (It's the exceptions that merit explicit direction.) JTW> Having said that, treating a UART RXD signal as a global clock sounds > rather bizarre. > > -Jeff
WHAT SITUATION I NEED A BUFFER
Started by ●August 7, 2006
Reply by ●August 8, 20062006-08-08
Reply by ●August 9, 20062006-08-09
Not sure if this really helps but a few years ago I saw a problem that was remarkably similar in concept. The PC application would lock up after transferring a significant, but random amount of data to the FPGA via a serial connection. The FPGA uart was one of the free cores on the xilinx site. It turned out the receive data line into the FPGA uart was not being synchronised to the uart clock before being used in the uart. As a result the FPGA uart would occasionally get into a locked up state. (no excuse for the PC app locking up though). Fix was simply to add a flop synchornising the rxd to the uart clock. ZHI wrote:> My algorithm is to solve the linear equation R.h=b, (R matrix ,b vector > is known, generated in Matlab). R,b are transmitted to FPGA board. > After the application caculation, h is sent back to Matlab. > I set the number of trials is 100. it will no problem. If > trials=100000, it will happen the "accidently stop" in Matlab. > I guess you are right that it looks like memory leak. I tried a simple > test. > Numbers from 1 to 100 transmit from Matlab to FPGA board(UART) and send > them back. These numbers are sent back correctly. If i send the number > from 1 to 1000 to UART. The matlab will show like that: > (InputBufferSize=512 in my matlab version) > ---------------------------------------------------------------- > Error using ==> serial.fread > SIZE * PRECISION must be less than or equal to InputBufferSize. > Error in ==> testuart at 17 > y= fread(s,1000,'uint8'); > ------------------------------------------------------- > I am not sure if i say it clearly. Hope you can help me to figure it > out. > Thanks a lot. > > Zhi > >
Reply by ●August 9, 20062006-08-09
That problem is not solved yet. I did add one D flip-flop before RXD. I
copied parts UART code here. Please give me some comment. Is this
problem i put the wrong flip-flop.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- UART MODUEL : BAUD RATE 115200 BPS
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity UARTNOBUF is
PORT(
SYSCLK : IN std_logic; --100 MHz from DCM
RS232_CTS_OUT : OUT std_logic;
RS232_RTS_IN : IN std_logic;
RS232_RX_DATA : IN std_logic;
RS232_TX_DATA : OUT std_logic;
RESET : IN std_logic;
READ : IN std_logic;
WRITE : IN std_logic;
DATAIN : OUT std_logic_vector(7 downto 0);
DATAOUT : IN std_logic_vector(7 downto 0);
RXRDY : OUT std_logic;
TXRDY : OUT std_logic;
parityerr : OUT std_logic;
framingerr : OUT std_logic
); --detail comments about these port, refer to
wrlogic component.
end UARTNOBUF;
architecture Behavioral of UARTNOBUF is
SIGNAL CLKX16 : std_ulogic;
SIGNAL TX,RX : std_logic;
SIGNAL txhold,txreg : std_logic_vector(7 DOWNTO
0); -- not dataintmp
SIGNAL txtag1,txtag2,txparity,TXCLK,TXDONE,paritycycle,txdatardy :
std_logic; -- tag bits for detecting
SIGNAL rxhold,rxreg : std_logic_vector(7 DOWNTO 0);-- Holds received
data for read
SIGNAL rxparity,paritygen,
rxstop,rxclk,rxidle,rxdatardy : std_logic; -- Parity bit of received
data
SIGNAL div2, div27a, div27b, LUTOUT : std_logic;
-----------------------------------------------------
signal writeb,readb,txrdyb : std_logic;
-----------------------------------------------------
signal txclkb,rxclkb : std_logic;
begin
rxdinst: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => rx,
C => SYSCLK,
CE => '1',
CLR => '0',
D => RS232_RX_DATA
);
txinst: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register
('0')
PORT MAP (
Q => RS232_TX_DATA,
C => SYSCLK,
CE => '1',
CLR => '0',
D =>tx
);
writebuf: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => writeb, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => write -- Data input
);
readbuf: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => readb, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => read -- Data input
);
RXRDYBUF: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => rxrdy, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => rxdatardy -- Data input
);
TXRDYBUF: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => txrdy, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => txrdyb -- Data input
);
------------------------------------------------------------------------------------------
--**************************************** BAUDRATE GENERATOR
************************************************************
-- use shift register and LUT to do the clock divide
clkprescale1: SRL16E --divide the signal with 27-- 16+11
GENERIC MAP (INIT => X"0000")
PORT MAP (
Q => div27a,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1', --A = 1111, 16 bits
CE => '1',
CLK => SYSCLK,
D => div27b
);
clkprescale2: SRL16E --divide the signal with 27-- 16+11
GENERIC MAP (INIT => X"0001")
PORT MAP (
Q => div27b,
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '1', --A = 1010, 11 bits
CE => '1',
CLK => SYSCLK,
D => div27a
);
clkprescale3: SRL16E --divide the signal with 2
GENERIC MAP (INIT => X"0001")
PORT MAP (
Q => div2,
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0', --A = 0001, 2 bits
CE => div27b, --using div27 as the enable signal
CLK => SYSCLK,
D => div2
);
LUT2_inst : LUT2
generic map ( INIT => X"9")
port map (
O => LUTOUT, -- LUT general output
I0 => div27b, -- LUT input
I1 => div2 -- LUT input
);
clkdiv1: FDCE
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => CLKX16, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => LUTOUT-- Data input
);
--**************************************** TRANSMITTING
************************************************************
...............................................................
Reply by ●August 9, 20062006-08-09
THANKS ALL YOUR HELP. But this problem is not solved yet. I copied
part uart codes here. (This UART works well. I add some D-flip flop
before some signals ) Please point out what cause my maltalb would be
locked up.
---------------------------------------------------------------------------------------------------
-- UART MODUEL : BAUD RATE 115200 BPS
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity UARTNOBUF is
PORT(
SYSCLK : IN std_logic; --100 MHz from DCM
RS232_CTS_OUT : OUT std_logic;
RS232_RTS_IN : IN std_logic;
RS232_RX_DATA : IN std_logic;
RS232_TX_DATA : OUT std_logic;
RESET : IN std_logic;
READ : IN std_logic;
WRITE : IN std_logic;
DATAIN : OUT std_logic_vector(7 downto 0);
DATAOUT : IN std_logic_vector(7 downto 0);
RXRDY : OUT std_logic;
TXRDY : OUT std_logic;
parityerr : OUT std_logic;
framingerr : OUT std_logic
); --detail comments about these port, refer to
wrlogic component.
end UARTNOBUF;
architecture Behavioral of UARTNOBUF is
SIGNAL CLKX16 : std_ulogic;
SIGNAL TX,RX : std_logic;
SIGNAL txhold,txreg : std_logic_vector(7 DOWNTO
0); -- not dataintmp
SIGNAL txtag1,txtag2,txparity,TXCLK,TXDONE,paritycycle,txdatardy :
std_logic; -- tag bits for detecting
SIGNAL rxhold,rxreg : std_logic_vector(7 DOWNTO 0);-- Holds received
data for read
SIGNAL rxparity,paritygen,
rxstop,rxclk,rxidle,rxdatardy : std_logic; -- Parity bit of received
data
SIGNAL div2, div27a, div27b, LUTOUT : std_logic;
-----------------------------------------------------
signal writeb,readb,txrdyb : std_logic;
-----------------------------------------------------
signal txclkb,rxclkb : std_logic;
begin
rxdinst: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => rx,
C => SYSCLK,
CE => '1',
CLR => '0',
D => RS232_RX_DATA
);
txinst: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register
('0')
PORT MAP (
Q => RS232_TX_DATA,
C => SYSCLK,
CE => '1',
CLR => '0',
D =>tx
);
writebuf: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => writeb, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => write -- Data input
);
readbuf: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => readb, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => read -- Data input
);
RXRDYBUF: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => rxrdy, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => rxdatardy -- Data input
);
TXRDYBUF: FDCE_1
GENERIC MAP (INIT => '0') -- Initial value of register ('0')
PORT MAP (
Q => txrdy, -- Data output
C => SYSCLK, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => txrdyb -- Data input
);
------------------------------------------------------------------------------------------
--**************************************** BAUDRATE GENERATOR
************************************************************
-----------------------------------------------------------------------------------
jtw wrote:
> "Jeff Cunningham" <jcc@sover.net> wrote in message
> news:44d7f7d1$0$6591$4d3efbfe@news.sover.net...
> > ZHI wrote:
> >> Thanks Mike Treseler
> >> I am not reading a vhdl netlist. I am reading a uart application
> >> codes. For example, the input signal (RXD signal) of FPGA firstly
> >> go through a IBUF then a BUFG. What's the uses of them respectively?
> >> Why need use these buffers? When need use them?
> >> Or we actually don't need to care these buffers at all.
> >
> > BUFG is a buffer which drives a global clock network.
> > IBUF is a buffer from the input pin.
> >
> > IBUF->BUFG would typically be used when an external pin is used to drive a
> > clock signal and the pin is NOT a dedicated clock input.
> >
> > Ideally a synthesizer would handle this automatically. Sometimes the tool
> > is not smart enough. Instantiating BUFG directly forces it to route the
> > signal on a global clock net.
> >
> Sometimes the tool is too smart, and sometimes what you need cannot be
> properly inferred.
>
> In a multiple clock design, I prefer to direct which clocks get which
> bufg's. I may also want to direct the naming to facilitate placement
> control in the constraints file. There are many potential reasons for doing
> direct VHDL instantation of a specific component.
>
> Nevertheless, I have difficulty with the idea of explicity instantiating
> hundreds of IBUFs and OBUFs in my code. The tools have matured to the
> extent that those key pieces will be inferred and created in the edif
> netlist. (It's the exceptions that merit explicit direction.)
>
> JTW
> > Having said that, treating a UART RXD signal as a global clock sounds
> > rather bizarre.
> >
> > -Jeff
