Xilinx isnt advertizing 'small things' that are also coming as bonus with Virtex-5, I found one by accident while browsing the ML501 reference designs and docu, namly * Virtex-5 has fully dedicated pins for the parallel flash so any NOR flash connected properly as configuration memory is also accessible by the dedicated pins for both read and writes. Those it is possible to use indirect nor flash programming for V5-connected nor flash, and surprise it is already offered by Xilinx! its hidden in the "LAB resources" for ML501 but the indirect programming software and bitstreams are available for all v5lx devices. * anothes small thing is the access to configuration clock oscillator after configuration from FPGA fabric (but that has already been told here) * not to mention that the SYSMON what is there in V4 (but disabled by the tools) is now finally user accessible * CRC32 and CRC64 as primitives * EFUSE primitive whats that !? * KEYCLEAR primitive !! Thanks you, Xilinx! this is for clearing the encryption key from the FPGA fabric - I was missing this feature badly, now its there !! * PCIE primitive ? I am not believing what I am seeing ?! * PMV is still there too * USR_ACCESS is enhanced as well I guess there are some more nice small things hidden - anyone found something? or was I just dreaming? too late maybe I'd better rest or who knows what else I would be seeing! Antti
Virtex-5: small little things.
Started by ●September 27, 2006
Reply by ●September 28, 20062006-09-28
Hi Annti, I would call PCIexpress everything but "small little thing" Aurash Antti wrote:>Xilinx isnt advertizing 'small things' that are also coming as bonus >with Virtex-5, I found one by accident while browsing the ML501 >reference designs and docu, namly > >* Virtex-5 has fully dedicated pins for the parallel flash so any NOR >flash connected properly as configuration memory is also accessible by >the dedicated pins for both read and writes. Those it is possible to >use indirect nor flash programming for V5-connected nor flash, and >surprise it is already offered by Xilinx! its hidden in the "LAB >resources" for ML501 but the indirect programming software and >bitstreams are available for all v5lx devices. > >* anothes small thing is the access to configuration clock oscillator >after configuration from FPGA fabric (but that has already been told >here) > >* not to mention that the SYSMON what is there in V4 (but disabled by >the tools) is now finally user accessible > >* CRC32 and CRC64 as primitives > >* EFUSE primitive whats that !? > >* KEYCLEAR primitive !! Thanks you, Xilinx! this is for clearing the >encryption key from the FPGA fabric - I was missing this feature badly, >now its there !! > >* PCIE primitive ? I am not believing what I am seeing ?! > >* PMV is still there too > >* USR_ACCESS is enhanced as well > >I guess there are some more nice small things hidden - anyone found >something? >or was I just dreaming? too late maybe I'd better rest or who knows >what else >I would be seeing! > >Antti > > >-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
Reply by ●September 28, 20062006-09-28
Aurelian Lazarut wrote:> Hi Annti, > I would call PCIexpress everything but "small little thing" > AurashLooks like it's only the physical layer from the port name "PIPE..." Sylvain> Antti wrote: > >> Xilinx isnt advertizing 'small things' that are also coming as bonus >> with Virtex-5, I found one by accident while browsing the ML501 >> reference designs and docu, namly >> >> * Virtex-5 has fully dedicated pins for the parallel flash so any NOR >> flash connected properly as configuration memory is also accessible by >> the dedicated pins for both read and writes. Those it is possible to >> use indirect nor flash programming for V5-connected nor flash, and >> surprise it is already offered by Xilinx! its hidden in the "LAB >> resources" for ML501 but the indirect programming software and >> bitstreams are available for all v5lx devices. >> >> * anothes small thing is the access to configuration clock oscillator >> after configuration from FPGA fabric (but that has already been told >> here) >> >> * not to mention that the SYSMON what is there in V4 (but disabled by >> the tools) is now finally user accessible >> >> * CRC32 and CRC64 as primitives >> >> * EFUSE primitive whats that !? >> >> * KEYCLEAR primitive !! Thanks you, Xilinx! this is for clearing the >> encryption key from the FPGA fabric - I was missing this feature badly, >> now its there !! >> >> * PCIE primitive ? I am not believing what I am seeing ?! >> >> * PMV is still there too >> >> * USR_ACCESS is enhanced as well >> >> I guess there are some more nice small things hidden - anyone found >> something? >> or was I just dreaming? too late maybe I'd better rest or who knows >> what else >> I would be seeing! >> >> Antti >> >> >> > >
Reply by ●September 29, 20062006-09-29
Aurelian Lazarut schrieb:> Hi Annti, > I would call PCIexpress everything but "small little thing" > Aurash > Antti wrote: > > >Xilinx isnt advertizing 'small things' that are also coming as bonus > >with Virtex-5, I found one by accident while browsing the ML501 > >reference designs and docu, namly > > > >* Virtex-5 has fully dedicated pins for the parallel flash so any NOR > >flash connected properly as configuration memory is also accessible by > >the dedicated pins for both read and writes. Those it is possible to > >use indirect nor flash programming for V5-connected nor flash, and > >surprise it is already offered by Xilinx! its hidden in the "LAB > >resources" for ML501 but the indirect programming software and > >bitstreams are available for all v5lx devices. > > > >* anothes small thing is the access to configuration clock oscillator > >after configuration from FPGA fabric (but that has already been told > >here) > > > >* not to mention that the SYSMON what is there in V4 (but disabled by > >the tools) is now finally user accessible > > > >* CRC32 and CRC64 as primitives > > > >* EFUSE primitive whats that !? > > > >* KEYCLEAR primitive !! Thanks you, Xilinx! this is for clearing the > >encryption key from the FPGA fabric - I was missing this feature badly, > >now its there !! > > > >* PCIE primitive ? I am not believing what I am seeing ?! > > > >* PMV is still there too > > > >* USR_ACCESS is enhanced as well > > > >I guess there are some more nice small things hidden - anyone found > >something? > >or was I just dreaming? too late maybe I'd better rest or who knows > >what else > >I would be seeing! > > > >Antti > > > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324you are right I should have changed the subject line. initially i was only posting about the NOR flash indirect programming solution Antti http://www.microfpga.com
