Survey on Quartus SOPC/Nios-II

Chris schrieb:

> Glad I posted the question.  You guys are great.  So much info.
>
> I think the 8 bit micro is the right approach level:  PicoBlaze, Micro8.
> There is another PacoBlaze that looks interesting.  Probably others too.
> Waiting for info on ERIC5.
>
> The LatticeXP approach is attractive from a couple standpoints.  Being NV
> and single supply, if I can use the config clock in user mode, and keep some
> of my own extra data in the internal flash, than it becomes possible to do
> the whole implementation with a single part.  No regulators, no external
> flash, no xtal/osc.  Great for PCB routing and space.  Very slick and clean.
> One single part.  Might be able to use a double sided board.
>
> Need to talk to Lattice about a couple points there.  I think I can keep the
> config osc running by setting the PERSISTENT flag ON, but not sure about
> flash usage.   Otherwise Xilinx 3E-100 is probably best choice.
>
> Thanks guys!
>
> Chris.

in XP the config oscillator is NOT accessible.
but that is not a big deal at all, you can use in fabric oscillator
as well, works great I have tested with lattice XP as well

Antti

> Waiting for info on ERIC5.

Hi Chris,

I have seen that you have requested the ERIC5-datasheets & eval-kit on our 
homepage, you should have received it automatically via e-mail. Maybe the 
supplied e-mail address was incorrect (althought it looks plausible), or the 
mail was blocked by a firewall / spam-filter? If it really did not arrive, 
you can send me an e-mail.

Thomas 

> in XP the config oscillator is NOT accessible.

According to their sysCONFIG pdf, the CCLK is brought out to a pin.  If you
set the PERSISTENT flag to ON, then the config is suppose to keep alive.
Doesn't that mean that the CCLK will keep going?

> but that is not a big deal at all, you can use in fabric oscillator

I assume you mean the sysClock.  I saw that PLL but assumed it needed an
external input.

What about using the internal flash for read/write during user mode.  Any
experience with XP parts on that?

Thanks,  Chris.

Chris schrieb:

> > in XP the config oscillator is NOT accessible.
>
> According to their sysCONFIG pdf, the CCLK is brought out to a pin.  If you
> set the PERSISTENT flag to ON, then the config is suppose to keep alive.
> Doesn't that mean that the CCLK will keep going?
>
> > but that is not a big deal at all, you can use in fabric oscillator
>
> I assume you mean the sysClock.  I saw that PLL but assumed it needed an
> external input.
>
> What about using the internal flash for read/write during user mode.  Any
> experience with XP parts on that?
>
> Thanks,  Chris.

no, I did mean the CCLK "inside" the FPGA, the config osc primitive is
visible in devive viewer but the primitive cant be used in XP, it can
used in ECP
and some other lattice fpgas

there is no user flash, but if you mean the flash config that is
rewriteable
but you need to wire loop jtag pins to user io

Antti

> no, I did mean the CCLK "inside" the FPGA, the config osc primitive is
> visible in devive viewer but the primitive cant be used in XP, it can
> used in ECP
> and some other lattice fpgas
>
> there is no user flash, but if you mean the flash config that is
> rewriteable
> but you need to wire loop jtag pins to user io

Exactly.  PERSISTENT=ON keeps the pins alive.  If I wire those around to
other IO pins, then I should be able to read/write to the Flash while
running and use the CCLK to run the CPU.

Chris.

Chris schrieb:

> > no, I did mean the CCLK "inside" the FPGA, the config osc primitive is
> > visible in devive viewer but the primitive cant be used in XP, it can
> > used in ECP
> > and some other lattice fpgas
> >
> > there is no user flash, but if you mean the flash config that is
> > rewriteable
> > but you need to wire loop jtag pins to user io
>
> Exactly.  PERSISTENT=ON keeps the pins alive.  If I wire those around to
> other IO pins, then I should be able to read/write to the Flash while
> running and use the CCLK to run the CPU.
>
> Chris.

there is no need for persistant, the JTAG pins that you need are
available always
no matter config settings

just wire jtag to io and use ring oscillator, thats it

Antti

Nope won't work.  I talked to Lattice today.  There is no internal osc to
use, and they did not recommend using a bunch of gates.  Moreover there is
no extra flash space either - zip.  This is not the first time.  Overall I
am very disappointed with what they put out in their MachXO and XP  NV
families.  They lack a lot of little features that would make them so much
more powerful.  I guess they have heard that from others too, he told me
that they were coming out with a 'revised' new XP line next year.  XP-II I
think he said.

Chris.

Chris wrote:
> I am evaluating using the Altera Cyclone with Quartus SOPC vs. Xilinx
> Spartan3E and PicoBlaze.  I need a soft core processor and I think PicoBlaze
> would be enough.  SOPC and Nios-II is very powerful but the learning curve
> looks like a potential nightmare to me.  In order to use SOPC I might have
> to get involved writing custom components to do the job and then one has to
> master the Avalon interface.  That looks like a lot of potential debugging
> time.
> 
> The Xilinx solution seems more direct, and under my control, since PicoBlaze
> is stand alone and does not depend on so many bus interrelated components
> and SOPC infrastructure.  Easier and quicker to write direct interfaces.
> Nios seems to need much more of the SOPC (RAM,ROM,Avalon,etc) around it to
> work.
> 
> Also, it seems like the Nios/SOPC solution is likely to require far more
> gates than a Xilinx/PicoBlaze implementation.
> 
> I would be curious to know any of your experiences with SOPC/Nios-II.  I
> have very limited R&D time for this project.
> 
> Thanks,  Chris.
> 

If you don't need very tight integration between the processor and the 
FPGA, you might save yourself a great deal of time and effort by using 
an external small microcontroller.  Choose the right part, and things 
like I2C are a no-brainer.

Chris wrote:
> Nope won't work.  I talked to Lattice today.  There is no internal osc to
> use, and they did not recommend using a bunch of gates.  Moreover there is
> no extra flash space either - zip.  This is not the first time.  Overall I
> am very disappointed with what they put out in their MachXO and XP  NV
> families.  They lack a lot of little features that would make them so much
> more powerful.  I guess they have heard that from others too, he told me
> that they were coming out with a 'revised' new XP line next year.  XP-II I
> think he said.
>
> Chris.

Hello Chris,

I spoke with our Director of Applications, Bertrand Leigh on this topic
and confirmed that the application will work.

Antti is correct, you CAN build an internal ring oscillator based on
stacked inverters for a coarse frequency oscillator inside the XP or
EC/ECP type devices.  This is a proven method that has worked at
Lattice and at other users. XO and ECP2/M device families have built-in
oscillator based on the configuration oscillator that is accessable
from the FPGA fabric after configuration.

For Flash write back both options are available -- PERSISTENT=ON for
sysConfig port and through JTAG.

We will follow up with the person you spoke to on our technical support
line and let them know about this application. Sorry if they caused any
confusion.

Hope this helps.
Bart Borosky, Lattice Semiconductor

bart schrieb:

> Chris wrote:
> > Nope won't work.  I talked to Lattice today.  There is no internal osc to
> > use, and they did not recommend using a bunch of gates.  Moreover there is
> > no extra flash space either - zip.  This is not the first time.  Overall I
> > am very disappointed with what they put out in their MachXO and XP  NV
> > families.  They lack a lot of little features that would make them so much
> > more powerful.  I guess they have heard that from others too, he told me
> > that they were coming out with a 'revised' new XP line next year.  XP-II I
> > think he said.
> >
> > Chris.
>
> Hello Chris,
>
> I spoke with our Director of Applications, Bertrand Leigh on this topic
> and confirmed that the application will work.
>
> Antti is correct, you CAN build an internal ring oscillator based on
> stacked inverters for a coarse frequency oscillator inside the XP or
> EC/ECP type devices.  This is a proven method that has worked at
> Lattice and at other users. XO and ECP2/M device families have built-in
> oscillator based on the configuration oscillator that is accessable
> from the FPGA fabric after configuration.
>
> For Flash write back both options are available -- PERSISTENT=ON for
> sysConfig port and through JTAG.
>
> We will follow up with the person you spoke to on our technical support
> line and let them know about this application. Sorry if they caused any
> confusion.
>
> Hope this helps.
> Bart Borosky, Lattice Semiconductor

thanks Bart,

there are many ways to make a ring-oscillator, depends on the needs I
have one version that I call fgpa_safe  it is basd on 4 FF that use
only set  reset pins. This thing always delivers an "useable" clock for
given FPGA and works any synthesis tool, eg does not get optimized
away.

there can different other methods, which may be better but may require
special trick to fool the optimizer and may require LOC contraints to
get better repeated frequency. invertor chain may run too high
simetimes, as example for V4 special care has to be taken to get the
inverter chain frequency to be low enough to be useable.

in most cases the fgpa_safe oscillator is sufficient, is sure has large
difference in frequency as it will be routed by different paths each
time.

Antti