DDR SDRAM access with MPMC2, Databus Width

Hi all,

I'm working on a Virtex-4 FX12LC Design with PPC405 Core, SDRAM and
Multiport Memory Controller 2 (MPMC2 release 2006/08/31). The Memec
Development Board contains the Infineon DDR SDRAM HYB25D512160BC-6 (64
Mbyte, Databus 16 bit). I started the Design with BSB and
OPB_DDR_CNTLR, then replaced the DDR_CNTLR with the MPMC2 Core of from
"ml403_ddr_p_100mhz" and changed the Memory Width to 16 bit, Pin
Constraints etc. The MPMC2 is configured to hold only one PLB
connection, the remaining 7 ports are set to "None".
After the project was built, I tried to access the SDRAM Memory via a
simple C Application or XMD. The problem now is, that the memory
content seems to be mirrored every 32 bit. For example, when I write at
address 0x00000000  a 32 bit value  0xA5A5A5A5, the same value appears
at address 0x00000008. The same behavior between addresses 0x00000004
and 0x0000000C.

It looks like:
0x00000000: 0xA5A5A5A5  0x00000000 0xA5A5A5A5 0x00000000
0x00000010: 0x00000000  0xDEADBEEF 0x00000000 0xDEADBEEF
0x00000020: 0x00001111  0x00002222 0x00001111 0x00002222
0x00000030: 0x00000000  0x00000000 0x00000000 0x00000000

The MPMC Part in system.mhs:

BEGIN mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6
 PARAMETER INSTANCE = mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6_0
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_PLB_0_BASEADDR = 0x0000_0000
 PARAMETER C_PLB_0_HIGHADDR = 0x03ff_ffff
 PARAMETER C_PLB_0_PLB_NUM_MASTERS = 2
 PARAMETER C_PLB_0_PLB_MID_WIDTH = 1
 PARAMETER C_PLB_0_PI_TO_MPMC2_CLK_RATIO = 1
 PARAMETER C_PLB_0_MPMC2_TO_PI_CLK_RATIO = 1
 PARAMETER C_PLB_0_BRIDGE_TO_PI_CLK_RATIO = 1
 BUS_INTERFACE PLB_S_0 = plb
 PORT MPMC2_0_Rst = sys_bus_reset
 PORT PLB_0_PLB_SlClk = CLK_100MHz
 PORT MPMC2_0_Clk0_2X = net_gnd
 PORT MPMC2_Slowest_Clk = CLK_100MHz
 PORT MPMC2_0_Clk0 = CLK_100MHz
 PORT MPMC2_0_Clk90 = CLK_100MHz_90
 PORT MPMC2_0_Clk_Cal = CLK_100MHz
 PORT MPMC2_0_Clk_200MHz = CLK_200MHz
 PORT MPMC2_0_Clk_Mem = CLK_100MHz_90
 PORT MPMC2_0_DDR_Clk_O = DDR_Clk
 PORT MPMC2_0_DDR_Clk_n_O = DDR_Clkn
 PORT MPMC2_0_DDR_CE_O = DDR_CKE
 PORT MPMC2_0_DDR_BankAddr_O = DDR_BA
 PORT MPMC2_0_DDR_Addr_O = DDR_Addr
 PORT MPMC2_0_DDR_CS_n_O = DDR_CSn
 PORT MPMC2_0_DDR_RAS_n_O = DDR_RASn
 PORT MPMC2_0_DDR_CAS_n_O = DDR_CASn
 PORT MPMC2_0_DDR_WE_n_O = DDR_WEn
 PORT MPMC2_0_DDR_DQ = DDR_DQ
 PORT MPMC2_0_DDR_DQS = DDR_DQS
 PORT MPMC2_0_DDR_DM = DDR_DM
END

The MPMC parameters are equal to the reference design
"v4fx12lc_ddr_idpp_100mhz", except the parameters which setup the
number of master/slaves, and of course the datawidth of memory. I
checked the pin constraints, they are ok.
So where could be the mistake? Are there any MPMC Parameters which I
forgot to set correctly? Do I need to modify PLB Settings?

Are there any suggestions or hints?
Thanks in advance.
Mack

Mack,

Does your board have only one memory chip? If there are 2 chips then your
memory bus width should probably be 32 bits. I doubt the MPMC2 was ever
tested with 16-bit memory.

/Mikhail

Hi Mack,

What about:  PARAMETER C_PLB_0_PLB_NUM_MASTERS = 2 - is that correct.
Mine GSRD2 desing (MPMC2 based) works fine on Virtex-4 FX12 Mini Module
and it basically the same platform.
Use the MPMC2 GUI to generate custom MPMC2 core!!

Guru

Mack wrote:
> Hi all,
>
> I'm working on a Virtex-4 FX12LC Design with PPC405 Core, SDRAM and
> Multiport Memory Controller 2 (MPMC2 release 2006/08/31). The Memec
> Development Board contains the Infineon DDR SDRAM HYB25D512160BC-6 (64
> Mbyte, Databus 16 bit). I started the Design with BSB and
> OPB_DDR_CNTLR, then replaced the DDR_CNTLR with the MPMC2 Core of from
> "ml403_ddr_p_100mhz" and changed the Memory Width to 16 bit, Pin
> Constraints etc. The MPMC2 is configured to hold only one PLB
> connection, the remaining 7 ports are set to "None".
> After the project was built, I tried to access the SDRAM Memory via a
> simple C Application or XMD. The problem now is, that the memory
> content seems to be mirrored every 32 bit. For example, when I write at
> address 0x00000000  a 32 bit value  0xA5A5A5A5, the same value appears
> at address 0x00000008. The same behavior between addresses 0x00000004
> and 0x0000000C.
>
> It looks like:
> 0x00000000: 0xA5A5A5A5  0x00000000 0xA5A5A5A5 0x00000000
> 0x00000010: 0x00000000  0xDEADBEEF 0x00000000 0xDEADBEEF
> 0x00000020: 0x00001111  0x00002222 0x00001111 0x00002222
> 0x00000030: 0x00000000  0x00000000 0x00000000 0x00000000
>
> The MPMC Part in system.mhs:
>
> BEGIN mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6
>  PARAMETER INSTANCE = mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6_0
>  PARAMETER HW_VER = 1.04.a
>  PARAMETER C_PLB_0_BASEADDR = 0x0000_0000
>  PARAMETER C_PLB_0_HIGHADDR = 0x03ff_ffff
>  PARAMETER C_PLB_0_PLB_NUM_MASTERS = 2
>  PARAMETER C_PLB_0_PLB_MID_WIDTH = 1
>  PARAMETER C_PLB_0_PI_TO_MPMC2_CLK_RATIO = 1
>  PARAMETER C_PLB_0_MPMC2_TO_PI_CLK_RATIO = 1
>  PARAMETER C_PLB_0_BRIDGE_TO_PI_CLK_RATIO = 1
>  BUS_INTERFACE PLB_S_0 = plb
>  PORT MPMC2_0_Rst = sys_bus_reset
>  PORT PLB_0_PLB_SlClk = CLK_100MHz
>  PORT MPMC2_0_Clk0_2X = net_gnd
>  PORT MPMC2_Slowest_Clk = CLK_100MHz
>  PORT MPMC2_0_Clk0 = CLK_100MHz
>  PORT MPMC2_0_Clk90 = CLK_100MHz_90
>  PORT MPMC2_0_Clk_Cal = CLK_100MHz
>  PORT MPMC2_0_Clk_200MHz = CLK_200MHz
>  PORT MPMC2_0_Clk_Mem = CLK_100MHz_90
>  PORT MPMC2_0_DDR_Clk_O = DDR_Clk
>  PORT MPMC2_0_DDR_Clk_n_O = DDR_Clkn
>  PORT MPMC2_0_DDR_CE_O = DDR_CKE
>  PORT MPMC2_0_DDR_BankAddr_O = DDR_BA
>  PORT MPMC2_0_DDR_Addr_O = DDR_Addr
>  PORT MPMC2_0_DDR_CS_n_O = DDR_CSn
>  PORT MPMC2_0_DDR_RAS_n_O = DDR_RASn
>  PORT MPMC2_0_DDR_CAS_n_O = DDR_CASn
>  PORT MPMC2_0_DDR_WE_n_O = DDR_WEn
>  PORT MPMC2_0_DDR_DQ = DDR_DQ
>  PORT MPMC2_0_DDR_DQS = DDR_DQS
>  PORT MPMC2_0_DDR_DM = DDR_DM
> END
>
> The MPMC parameters are equal to the reference design
> "v4fx12lc_ddr_idpp_100mhz", except the parameters which setup the
> number of master/slaves, and of course the datawidth of memory. I
> checked the pin constraints, they are ok.
> So where could be the mistake? Are there any MPMC Parameters which I
> forgot to set correctly? Do I need to modify PLB Settings?
> 
> Are there any suggestions or hints?
> Thanks in advance.
> Mack

@Guru: I think PARAMETER C_PLB_0_PLB_NUM_MASTERS=3D2 is correct, when i
set the value to 1, then i get the implementation error:
logical net 'plb_Sl_MBusy<1>' has multiple driver(s):
     pin O on block plb2opb/plb2opb/BGO_MBusy<1>1 with type LUT3,
     pin O on block
mpmc2_ddr_p_100mhz_x16_hyb25d512160bc_6_0/mpmc2_ddr_p_100mhz_x16_hyb25d5121=
60bc_6_0/mpmc2_plb_if_0/_n08872
with type LUT2

@MM: There is only one memory chip on my eval board, so the databus
should be 16 bit.
Now i worked out that the original mpmc2 reference design
"v4fx12lc_ddr_idpp_100mhz" also have this memory problem. The same
behaviour, a write to 0x0 also appears at 0x0+8. I built it as a blank
XPS design importing system.mhs, system.ucf files and ipcores.
Now I=B4m quite confused if it is principally possible to interface a 16
bit memory correctly. I suppose there could be wrong parameter
settings.


Mack

>@MM: There is only one memory chip on my eval board, so the databus
>should be 16 bit.
>Now i worked out that the original mpmc2 reference design
>"v4fx12lc_ddr_idpp_100mhz" also have this memory problem. The same
>behaviour, a write to 0x0 also appears at 0x0+8. I built it as a blank
>XPS design importing system.mhs, system.ucf files and ipcores.
>Now I�m quite confused if it is principally possible to interface a 16
>bit memory correctly. I suppose there could be wrong parameter
>settings.

Any change to the MPMC2 has to be done with the GUI. It is not clear from
your posts whether you actually ran the GUI to modify the controller or if
you simply hacked the MHS file... The GUI seems to allow 16-bit wide
memory...

/Mikhail

Hi,

I generated my MPMC2 Core with the GUI 1.6. I took a preconfigured core
"ml403_ddr_p_100mhz" and changed the memory style, type, part width
etc. so that it fits to my board memory (Infineon HYB25D512160BC) and
modified the Number of Data Pins in the Memory Settings to 16. After
that I generated the Core. The Arbiter Algorithm didn=B4t need to be
changed.

In XPS I ran the BSB Wizard to build a project with OPB_DDR Controller
and some peripheral parts, checked it with the simple TestMemory_App,
everything ok. Rescan User Repositories. Then I added the MPMC2 and
dcm_por_reset IPs and connected the Ports etc as described in MPMC2
release notes by editing the mhs file. I also removed the opb_ddr
instance. After that I build the project, downloaded bitstream and
checked per xmd the memory state, there I have this problem mentioned
above.

Any other suggestions?
Thanks,
Mack

> Any other suggestions?

I believe The MPMC2 zip has two projects using 16-bit memory:
v4fx12lc_ddr_idpp_100mhz
v4fx12mm_ddr_idpp_100mhz

I found this info in the release notes... Take a look at these cores...

/Mikhail