Hi, I have a design in which I need to instantiate two microblaze system instances (the same microblaze system in two places). I'm doing it by the following way: 1) I've created a system containing a single microblaze (in EDK) 2) I've instantiated it in my hdl code in two different places. 3) Then I merged the two bmm files into a single bmm file which looks like this: /////////////////////////////////////////////////////////////////////////////// // // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). // /////////////////////////////////////////////////////////////////////////////// ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] BUS_BLOCK CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; /////////////////////////////////////////////////////////////////////////////// // // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). // /////////////////////////////////////////////////////////////////////////////// ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] BUS_BLOCK CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; 4) I synthesize my design using synplify 8.1 5) I call the following script (for translate and map) ngdbuild -a -p XC4VLX80-FF1148-10 -bm /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tmac.bmm -sd ../../../../syn/syn_v4/edf -uc ../../bs_lx80.ucf bs rev1/bs.ngd; map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b rev1/bs.ngd rev1/bs.pcf; The ngdbuild goes well but the mapping process has lots of errors ( it seems that the mapper tries to place the two microblaze instances on top of each other) part of the map log file (.mrp) is attached Can you please advise ? Thanks in advance, Mordehay. Snippet of the map report file (originaly conatins 465 errors): Release 7.1.03i Map H.41 Xilinx Mapping Report File for Design 'bs' Design Information ------------------ Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b rev1/bs.ngd rev1/bs.pcf Target Device : xc4vlx80 Target Package : ff1148 Target Speed : -10 Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ Mapped Date : Mon Nov 6 11:55:10 2006 Design Summary -------------- Number of errors : 465 Number of warnings :3074 Section 1 - Errors ------------------ ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y0) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y1) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y2) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y3) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y0) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y4) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y1) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT31" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<31>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT31" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<31>) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y5) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y2) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write<15>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write<15>) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y6) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y3) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT15" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<15>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT15" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<15>) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y7) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y4) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y8) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X2Y0) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg2_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg2_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y9) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. and it continues like this ....
To Xilinx guys out there - microblaze mapping problem
Started by ●November 6, 2006
Reply by ●November 6, 20062006-11-06
Hi, The problem is that the two microblazes have the exact same name. MicroBlaze is a RLOC block which requires a unique name. In this case, I think you need to create two EDK designs which are more or less the same except for the instance name of MicroBlaze or you can also create two microblaze in one EDK design. G�ran <me_2003@walla.co.il> wrote in message news:1162808786.323369.313200@h48g2000cwc.googlegroups.com...> Hi, > I have a design in which I need to instantiate two microblaze system > instances (the same microblaze system in two places). > I'm doing it by the following way: > 1) I've created a system containing a single microblaze (in EDK) > 2) I've instantiated it in my hdl code in two different places. > 3) Then I merged the two bmm files into a single bmm file which looks > like this: > > /////////////////////////////////////////////////////////////////////////////// > // > // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > // > /////////////////////////////////////////////////////////////////////////////// > > ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > BUS_BLOCK > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > END_BUS_BLOCK; > END_ADDRESS_BLOCK; > > /////////////////////////////////////////////////////////////////////////////// > // > // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > // > /////////////////////////////////////////////////////////////////////////////// > > ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > BUS_BLOCK > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > END_BUS_BLOCK; > END_ADDRESS_BLOCK; > > 4) I synthesize my design using synplify 8.1 > 5) I call the following script (for translate and map) > > ngdbuild -a -p XC4VLX80-FF1148-10 -bm > /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tmac.bmm > -sd ../../../../syn/syn_v4/edf > -uc ../../bs_lx80.ucf bs rev1/bs.ngd; > > map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b > rev1/bs.ngd rev1/bs.pcf; > > The ngdbuild goes well but the mapping process has lots of errors ( it > seems that the mapper tries to place the two microblaze instances on > top of each other) > part of the map log file (.mrp) is attached > Can you please advise ? > Thanks in advance, Mordehay. > > Snippet of the map report file (originaly conatins 465 errors): > > Release 7.1.03i Map H.41 > Xilinx Mapping Report File for Design 'bs' > > Design Information > ------------------ > Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o > rev1/map.ncd -pr > b rev1/bs.ngd rev1/bs.pcf > Target Device : xc4vlx80 > Target Package : ff1148 > Target Speed : -10 > Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ > Mapped Date : Mon Nov 6 11:55:10 2006 > > Design Summary > -------------- > Number of errors : 465 > Number of warnings :3074 > > Section 1 - Errors > ------------------ > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y0) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I31/reg1_Data_Low) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I31/reg1_Data_Low) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y1) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I31/reg1_Data_High) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I31/reg1_Data_High) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y2) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I15/reg1_Data_Low) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I15/reg1_Data_Low) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y3) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I15/reg1_Data_High) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I15/reg1_Data_High) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X1Y0) which require the combination of the following symbols > into a > single SLICE component: > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) > There are more than two function generators. Please correct the > design > constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y4) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I30/reg1_Data_Low) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I30/reg1_Data_Low) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X1Y1) which require the combination of the following symbols > into a > single SLICE component: > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > Mux_I1/MUX_LUT31" (Output Signal = > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > Mux_I1/MUX_LUT31" (Output Signal = > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) > There are more than two function generators. Please correct the > design > constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y5) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I30/reg1_Data_High) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I30/reg1_Data_High) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X1Y2) which require the combination of the following symbols > into a > single SLICE component: > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > There are more than two function generators. Please correct the > design > constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y6) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I14/reg1_Data_Low) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I14/reg1_Data_Low) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X1Y3) which require the combination of the following symbols > into a > single SLICE component: > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > Mux_I1/MUX_LUT15" (Output Signal = > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > Mux_I1/MUX_LUT15" (Output Signal = > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) > There are more than two function generators. Please correct the > design > constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y7) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I14/reg1_Data_High) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I14/reg1_Data_High) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X1Y4) which require the combination of the following symbols > into a > single SLICE component: > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) > LUT symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) > LUT symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) > There are more than two function generators. Please correct the > design > constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y8) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I29/reg1_Data_Low) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I29/reg1_Data_Low) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X2Y0) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I31/reg2_Data_Low) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I31/reg2_Data_Low) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > ERROR:Pack:679 - Unable to obey design constraints > (MACRONAME=microblaze_0, > RLOC=X0Y9) which require the combination of the following symbols > into a > single SLICEM component: > RAMDP symbol > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I29/reg1_Data_High) > RAMDP symbol > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > /Register_File_Bit_I29/reg1_Data_High) > The address signals must match exactly when using both F and G in > RAM mode. > Please correct the design constraints accordingly. > > and it continues like this .... >
Reply by ●November 6, 20062006-11-06
Hi Goran, Is there any way to instruct the platgen not to use RLOC for the microblaze? It is just that now (after doing what you suggested above) my mapping went well but the PAR fails - It says that a certain core (xilinx reed-solomon decoder) cannot be placed. I figured out that maybe the RLOCs of the microblaze causes this problem (my chip utilization is under 50%). Thanks in advance, Mordehay. error snippet from par log file : ---------------------------------------------------------------------------= ----------------------------------------------- Starting Placer Phase 1.1 ERROR:Place:346 - The components related to The RPM "CORE/RFEC_i/rs_dec_i/rs_docoder_i/rs_dec/dec/sy/nig1/ffo1/r1" can not be placed in the required relative placement form The following components are part of this structure: SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N207 SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19412 SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19411 SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19409 SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N208 SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N204 SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N202 The reason for this issue is the following: This logic may be too large or of too irregular shape to fit on the device. ---------------------------------------------------------------------------= ----------------------------------------------- G=F6ran Bilski wrote:> Hi, > > The problem is that the two microblazes have the exact same name. > MicroBlaze is a RLOC block which requires a unique name. > > In this case, I think you need to create two EDK designs which are more or > less the same except for the instance name of MicroBlaze > or you can also create two microblaze in one EDK design. > > G=F6ran > > <me_2003@walla.co.il> wrote in message > news:1162808786.323369.313200@h48g2000cwc.googlegroups.com... > > Hi, > > I have a design in which I need to instantiate two microblaze system > > instances (the same microblaze system in two places). > > I'm doing it by the following way: > > 1) I've created a system containing a single microblaze (in EDK) > > 2) I've instantiated it in my hdl code in two different places. > > 3) Then I merged the two bmm files into a single bmm file which looks > > like this: > > > > ///////////////////////////////////////////////////////////////////////=////////> > // > > // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > // > > ///////////////////////////////////////////////////////////////////////=////////> > > > ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > BUS_BLOCK > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > END_BUS_BLOCK; > > END_ADDRESS_BLOCK; > > > > ///////////////////////////////////////////////////////////////////////=////////> > // > > // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > // > > ///////////////////////////////////////////////////////////////////////=////////> > > > ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > BUS_BLOCK > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > END_BUS_BLOCK; > > END_ADDRESS_BLOCK; > > > > 4) I synthesize my design using synplify 8.1 > > 5) I call the following script (for translate and map) > > > > ngdbuild -a -p XC4VLX80-FF1148-10 -bm > > /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tmac.b=mm> > -sd ../../../../syn/syn_v4/edf > > -uc ../../bs_lx80.ucf bs rev1/bs.ngd; > > > > map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b > > rev1/bs.ngd rev1/bs.pcf; > > > > The ngdbuild goes well but the mapping process has lots of errors ( it > > seems that the mapper tries to place the two microblaze instances on > > top of each other) > > part of the map log file (.mrp) is attached > > Can you please advise ? > > Thanks in advance, Mordehay. > > > > Snippet of the map report file (originaly conatins 465 errors): > > > > Release 7.1.03i Map H.41 > > Xilinx Mapping Report File for Design 'bs' > > > > Design Information > > ------------------ > > Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o > > rev1/map.ncd -pr > > b rev1/bs.ngd rev1/bs.pcf > > Target Device : xc4vlx80 > > Target Package : ff1148 > > Target Speed : -10 > > Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ > > Mapped Date : Mon Nov 6 11:55:10 2006 > > > > Design Summary > > -------------- > > Number of errors : 465 > > Number of warnings :3074 > > > > Section 1 - Errors > > ------------------ > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y0) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I31/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I31/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y1) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I31/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I31/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y2) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I15/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I15/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y3) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I15/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I15/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX1Y0) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data=<31>)> > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data=<31>)> > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal =3D > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal =3D > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) > > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y4) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I30/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I30/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX1Y1) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB=_Data_> > Mux_I1/MUX_LUT31" (Output Signal =3D > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB=_Data_> > Mux_I1/MUX_LUT31" (Output Signal =3D > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data=<31>)> > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data=<31>)> > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y5) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I30/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I30/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX1Y2) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data=<15>)> > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data=<15>)> > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y6) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I14/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I14/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX1Y3) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB=_Data_> > Mux_I1/MUX_LUT15" (Output Signal =3D > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB=_Data_> > Mux_I1/MUX_LUT15" (Output Signal =3D > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data=<15>)> > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data=<15>)> > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y7) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I14/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I14/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX1Y4) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal =3D > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal =3D > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data=<30>)> > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data=<30>)> > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y8) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I29/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I29/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX2Y0) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I31/reg2_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I31/reg2_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=3Dmicroblaze_0, > > RLOC=3DX0Y9) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I29/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register=_File_> > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_=File_I> > /Register_File_Bit_I29/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > > > and it continues like this .... > >
Reply by ●November 7, 20062006-11-07
Hi, There is no way to tell MicroBlaze not to use RLOC. You can however tell the ISE tools to ignore RLOCs. The map needs the parameter -ir G�ran <me_2003@walla.co.il> wrote in message news:1162829316.487307.248680@m73g2000cwd.googlegroups.com... Hi Goran, Is there any way to instruct the platgen not to use RLOC for the microblaze? It is just that now (after doing what you suggested above) my mapping went well but the PAR fails - It says that a certain core (xilinx reed-solomon decoder) cannot be placed. I figured out that maybe the RLOCs of the microblaze causes this problem (my chip utilization is under 50%). Thanks in advance, Mordehay. error snippet from par log file : -------------------------------------------------------------------------------------------------------------------------- Starting Placer Phase 1.1 ERROR:Place:346 - The components related to The RPM "CORE/RFEC_i/rs_dec_i/rs_docoder_i/rs_dec/dec/sy/nig1/ffo1/r1" can not be placed in the required relative placement form The following components are part of this structure: SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N207 SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19412 SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19411 SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19409 SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N208 SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N204 SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N202 The reason for this issue is the following: This logic may be too large or of too irregular shape to fit on the device. -------------------------------------------------------------------------------------------------------------------------- G�ran Bilski wrote:> Hi, > > The problem is that the two microblazes have the exact same name. > MicroBlaze is a RLOC block which requires a unique name. > > In this case, I think you need to create two EDK designs which are more or > less the same except for the instance name of MicroBlaze > or you can also create two microblaze in one EDK design. > > G�ran > > <me_2003@walla.co.il> wrote in message > news:1162808786.323369.313200@h48g2000cwc.googlegroups.com... > > Hi, > > I have a design in which I need to instantiate two microblaze system > > instances (the same microblaze system in two places). > > I'm doing it by the following way: > > 1) I've created a system containing a single microblaze (in EDK) > > 2) I've instantiated it in my hdl code in two different places. > > 3) Then I merged the two bmm files into a single bmm file which looks > > like this: > > > > /////////////////////////////////////////////////////////////////////////////// > > // > > // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > // > > /////////////////////////////////////////////////////////////////////////////// > > > > ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > BUS_BLOCK > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > END_BUS_BLOCK; > > END_ADDRESS_BLOCK; > > > > /////////////////////////////////////////////////////////////////////////////// > > // > > // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > // > > /////////////////////////////////////////////////////////////////////////////// > > > > ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > BUS_BLOCK > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > END_BUS_BLOCK; > > END_ADDRESS_BLOCK; > > > > 4) I synthesize my design using synplify 8.1 > > 5) I call the following script (for translate and map) > > > > ngdbuild -a -p XC4VLX80-FF1148-10 -bm > > /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tmac.bmm > > -sd ../../../../syn/syn_v4/edf > > -uc ../../bs_lx80.ucf bs rev1/bs.ngd; > > > > map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b > > rev1/bs.ngd rev1/bs.pcf; > > > > The ngdbuild goes well but the mapping process has lots of errors ( it > > seems that the mapper tries to place the two microblaze instances on > > top of each other) > > part of the map log file (.mrp) is attached > > Can you please advise ? > > Thanks in advance, Mordehay. > > > > Snippet of the map report file (originaly conatins 465 errors): > > > > Release 7.1.03i Map H.41 > > Xilinx Mapping Report File for Design 'bs' > > > > Design Information > > ------------------ > > Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o > > rev1/map.ncd -pr > > b rev1/bs.ngd rev1/bs.pcf > > Target Device : xc4vlx80 > > Target Package : ff1148 > > Target Speed : -10 > > Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ > > Mapped Date : Mon Nov 6 11:55:10 2006 > > > > Design Summary > > -------------- > > Number of errors : 465 > > Number of warnings :3074 > > > > Section 1 - Errors > > ------------------ > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y0) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I31/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I31/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y1) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I31/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I31/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y2) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I15/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I15/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y3) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I15/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I15/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X1Y0) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) > > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y4) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I30/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I30/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X1Y1) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > > Mux_I1/MUX_LUT31" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > > Mux_I1/MUX_LUT31" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) > > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y5) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I30/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I30/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X1Y2) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y6) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I14/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I14/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X1Y3) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > > Mux_I1/MUX_LUT15" (Output Signal = > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > > Mux_I1/MUX_LUT15" (Output Signal = > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) > > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y7) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I14/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I14/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X1Y4) which require the combination of the following symbols > > into a > > single SLICE component: > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) > > LUT symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) > > LUT symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) > > There are more than two function generators. Please correct the > > design > > constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y8) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I29/reg1_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I29/reg1_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X2Y0) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I31/reg2_Data_Low) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I31/reg2_Data_Low) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=microblaze_0, > > RLOC=X0Y9) which require the combination of the following symbols > > into a > > single SLICEM component: > > RAMDP symbol > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I29/reg1_Data_High) > > RAMDP symbol > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > /Register_File_Bit_I29/reg1_Data_High) > > The address signals must match exactly when using both F and G in > > RAM mode. > > Please correct the design constraints accordingly. > > > > and it continues like this .... > >
Reply by ●November 7, 20062006-11-07
Hi Goran, Thanks again for your response. when using the -ir option I managed to get my PAR right, but now I'm worried about the results of not using the RLOC constraints. Is there a danger that my design wont work properly now ? Thanks again, Mordehay. G=F6ran Bilski wrote:> Hi, > > There is no way to tell MicroBlaze not to use RLOC. > You can however tell the ISE tools to ignore RLOCs. > The map needs the parameter -ir > > G=F6ran > > > > <me_2003@walla.co.il> wrote in message > news:1162829316.487307.248680@m73g2000cwd.googlegroups.com... > Hi Goran, > > Is there any way to instruct the platgen not to use RLOC for the > microblaze? > It is just that now (after doing what you suggested above) my mapping > went well but the PAR fails - It says that a certain core (xilinx > reed-solomon decoder) cannot be placed. I figured out that maybe the > RLOCs of the microblaze causes this problem (my chip utilization is > under 50%). > Thanks in advance, Mordehay. > > error snippet from par log file : > > -------------------------------------------------------------------------=-------------------------------------------------> Starting Placer > > Phase 1.1 > ERROR:Place:346 - The components related to The RPM > "CORE/RFEC_i/rs_dec_i/rs_docoder_i/rs_dec/dec/sy/nig1/ffo1/r1" can > not be > placed in the required relative placement form > > The following components are part of this structure: > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N207 > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19412 > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19411 > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19409 > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N208 > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N204 > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N202 > > The reason for this issue is the following: > This logic may be too large or of too irregular shape to fit on the > device. > -------------------------------------------------------------------------=-------------------------------------------------> > > > > G=F6ran Bilski wrote: > > Hi, > > > > The problem is that the two microblazes have the exact same name. > > MicroBlaze is a RLOC block which requires a unique name. > > > > In this case, I think you need to create two EDK designs which are more=or> > less the same except for the instance name of MicroBlaze > > or you can also create two microblaze in one EDK design. > > > > G=F6ran > > > > <me_2003@walla.co.il> wrote in message > > news:1162808786.323369.313200@h48g2000cwc.googlegroups.com... > > > Hi, > > > I have a design in which I need to instantiate two microblaze system > > > instances (the same microblaze system in two places). > > > I'm doing it by the following way: > > > 1) I've created a system containing a single microblaze (in EDK) > > > 2) I've instantiated it in my hdl code in two different places. > > > 3) Then I merged the two bmm files into a single bmm file which looks > > > like this: > > > > > > /////////////////////////////////////////////////////////////////////=//////////> > > // > > > // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > > // > > > /////////////////////////////////////////////////////////////////////=//////////> > > > > > ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > > BUS_BLOCK > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > > END_BUS_BLOCK; > > > END_ADDRESS_BLOCK; > > > > > > /////////////////////////////////////////////////////////////////////=//////////> > > // > > > // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > > // > > > /////////////////////////////////////////////////////////////////////=//////////> > > > > > ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > > BUS_BLOCK > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > > END_BUS_BLOCK; > > > END_ADDRESS_BLOCK; > > > > > > 4) I synthesize my design using synplify 8.1 > > > 5) I call the following script (for translate and map) > > > > > > ngdbuild -a -p XC4VLX80-FF1148-10 -bm > > > /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tmac=.bmm> > > -sd ../../../../syn/syn_v4/edf > > > -uc ../../bs_lx80.ucf bs rev1/bs.ngd; > > > > > > map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b > > > rev1/bs.ngd rev1/bs.pcf; > > > > > > The ngdbuild goes well but the mapping process has lots of errors ( it > > > seems that the mapper tries to place the two microblaze instances on > > > top of each other) > > > part of the map log file (.mrp) is attached > > > Can you please advise ? > > > Thanks in advance, Mordehay. > > > > > > Snippet of the map report file (originaly conatins 465 errors): > > > > > > Release 7.1.03i Map H.41 > > > Xilinx Mapping Report File for Design 'bs' > > > > > > Design Information > > > ------------------ > > > Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o > > > rev1/map.ncd -pr > > > b rev1/bs.ngd rev1/bs.pcf > > > Target Device : xc4vlx80 > > > Target Package : ff1148 > > > Target Speed : -10 > > > Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ > > > Mapped Date : Mon Nov 6 11:55:10 2006 > > > > > > Design Summary > > > -------------- > > > Number of errors : 465 > > > Number of warnings :3074 > > > > > > Section 1 - Errors > > > ------------------ > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y0) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I31/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I31/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y1) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I31/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I31/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y2) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I15/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I15/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y3) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I15/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I15/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX1Y0) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Da=ta<31>)> > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Da=ta<31>)> > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal =3D > > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal =3D > > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) > > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y4) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I30/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I30/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX1Y1) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/O=PB_Data_> > > Mux_I1/MUX_LUT31" (Output Signal =3D > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/O=PB_Data_> > > Mux_I1/MUX_LUT31" (Output Signal =3D > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Da=ta<31>)> > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Da=ta<31>)> > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y5) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I30/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I30/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX1Y2) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Da=ta<15>)> > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Da=ta<15>)> > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y6) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I14/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I14/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX1Y3) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/O=PB_Data_> > > Mux_I1/MUX_LUT15" (Output Signal =3D > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/O=PB_Data_> > > Mux_I1/MUX_LUT15" (Output Signal =3D > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Da=ta<15>)> > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Da=ta<15>)> > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y7) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I14/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I14/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX1Y4) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal =3D > > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal =3D > > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Da=ta<30>)> > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Da=ta<30>)> > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y8) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I29/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I29/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX2Y0) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I31/reg2_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I31/reg2_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=3Dmicroblaze_0, > > > RLOC=3DX0Y9) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I29/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regist=er_File_> > > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Registe=r_File_I> > > /Register_File_Bit_I29/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > > > > and it continues like this .... > > >
Reply by ●November 7, 20062006-11-07
No, The only thing that might happen is that you will not reach the timing constraints. G�ran <me_2003@walla.co.il> wrote in message news:1162900739.332371.6350@m73g2000cwd.googlegroups.com... Hi Goran, Thanks again for your response. when using the -ir option I managed to get my PAR right, but now I'm worried about the results of not using the RLOC constraints. Is there a danger that my design wont work properly now ? Thanks again, Mordehay. G�ran Bilski wrote:> Hi, > > There is no way to tell MicroBlaze not to use RLOC. > You can however tell the ISE tools to ignore RLOCs. > The map needs the parameter -ir > > G�ran > > > > <me_2003@walla.co.il> wrote in message > news:1162829316.487307.248680@m73g2000cwd.googlegroups.com... > Hi Goran, > > Is there any way to instruct the platgen not to use RLOC for the > microblaze? > It is just that now (after doing what you suggested above) my mapping > went well but the PAR fails - It says that a certain core (xilinx > reed-solomon decoder) cannot be placed. I figured out that maybe the > RLOCs of the microblaze causes this problem (my chip utilization is > under 50%). > Thanks in advance, Mordehay. > > error snippet from par log file : > > -------------------------------------------------------------------------------------------------------------------------- > Starting Placer > > Phase 1.1 > ERROR:Place:346 - The components related to The RPM > "CORE/RFEC_i/rs_dec_i/rs_docoder_i/rs_dec/dec/sy/nig1/ffo1/r1" can > not be > placed in the required relative placement form > > The following components are part of this structure: > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N207 > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19412 > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19411 > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19409 > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N208 > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N204 > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N202 > > The reason for this issue is the following: > This logic may be too large or of too irregular shape to fit on the > device. > -------------------------------------------------------------------------------------------------------------------------- > > > > > G�ran Bilski wrote: > > Hi, > > > > The problem is that the two microblazes have the exact same name. > > MicroBlaze is a RLOC block which requires a unique name. > > > > In this case, I think you need to create two EDK designs which are more > > or > > less the same except for the instance name of MicroBlaze > > or you can also create two microblaze in one EDK design. > > > > G�ran > > > > <me_2003@walla.co.il> wrote in message > > news:1162808786.323369.313200@h48g2000cwc.googlegroups.com... > > > Hi, > > > I have a design in which I need to instantiate two microblaze system > > > instances (the same microblaze system in two places). > > > I'm doing it by the following way: > > > 1) I've created a system containing a single microblaze (in EDK) > > > 2) I've instantiated it in my hdl code in two different places. > > > 3) Then I merged the two bmm files into a single bmm file which looks > > > like this: > > > > > > /////////////////////////////////////////////////////////////////////////////// > > > // > > > // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > > // > > > /////////////////////////////////////////////////////////////////////////////// > > > > > > ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > > BUS_BLOCK > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > > END_BUS_BLOCK; > > > END_ADDRESS_BLOCK; > > > > > > /////////////////////////////////////////////////////////////////////////////// > > > // > > > // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > > // > > > /////////////////////////////////////////////////////////////////////////////// > > > > > > ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > > BUS_BLOCK > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > > END_BUS_BLOCK; > > > END_ADDRESS_BLOCK; > > > > > > 4) I synthesize my design using synplify 8.1 > > > 5) I call the following script (for translate and map) > > > > > > ngdbuild -a -p XC4VLX80-FF1148-10 -bm > > > /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tmac.bmm > > > -sd ../../../../syn/syn_v4/edf > > > -uc ../../bs_lx80.ucf bs rev1/bs.ngd; > > > > > > map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b > > > rev1/bs.ngd rev1/bs.pcf; > > > > > > The ngdbuild goes well but the mapping process has lots of errors ( it > > > seems that the mapper tries to place the two microblaze instances on > > > top of each other) > > > part of the map log file (.mrp) is attached > > > Can you please advise ? > > > Thanks in advance, Mordehay. > > > > > > Snippet of the map report file (originaly conatins 465 errors): > > > > > > Release 7.1.03i Map H.41 > > > Xilinx Mapping Report File for Design 'bs' > > > > > > Design Information > > > ------------------ > > > Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o > > > rev1/map.ncd -pr > > > b rev1/bs.ngd rev1/bs.pcf > > > Target Device : xc4vlx80 > > > Target Package : ff1148 > > > Target Speed : -10 > > > Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ > > > Mapped Date : Mon Nov 6 11:55:10 2006 > > > > > > Design Summary > > > -------------- > > > Number of errors : 465 > > > Number of warnings :3074 > > > > > > Section 1 - Errors > > > ------------------ > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y0) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I31/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I31/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y1) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I31/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I31/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y2) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I15/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I15/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y3) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I15/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I15/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X1Y0) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = > > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = > > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) > > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y4) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I30/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I30/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X1Y1) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > > > Mux_I1/MUX_LUT31" (Output Signal = > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > > > Mux_I1/MUX_LUT31" (Output Signal = > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<31>) > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) > > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y5) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I30/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I30/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X1Y2) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write<15>) > > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y6) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I14/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I14/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X1Y3) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > > > Mux_I1/MUX_LUT15" (Output Signal = > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ > > > Mux_I1/MUX_LUT15" (Output Signal = > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<15>) > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) > > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y7) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I14/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I14/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X1Y4) which require the combination of the following symbols > > > into a > > > single SLICE component: > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = > > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = > > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) > > > LUT symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) > > > LUT symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) > > > There are more than two function generators. Please correct the > > > design > > > constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y8) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I29/reg1_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I29/reg1_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X2Y0) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I31/reg2_Data_Low) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I31/reg2_Data_Low) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > ERROR:Pack:679 - Unable to obey design constraints > > > (MACRONAME=microblaze_0, > > > RLOC=X0Y9) which require the combination of the following symbols > > > into a > > > single SLICEM component: > > > RAMDP symbol > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I29/reg1_Data_High) > > > RAMDP symbol > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ > > > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I > > > /Register_File_Bit_I29/reg1_Data_High) > > > The address signals must match exactly when using both F and G in > > > RAM mode. > > > Please correct the design constraints accordingly. > > > > > > and it continues like this .... > > >
Reply by ●November 7, 20062006-11-07
Hi G=F6ran, Thanks a lot for your support - it was realy helpful.. Best regards, Mordehay. G=F6ran Bilski wrote:> No, The only thing that might happen is that you will not reach the timing > constraints. > > G=F6ran > > <me_2003@walla.co.il> wrote in message > news:1162900739.332371.6350@m73g2000cwd.googlegroups.com... > Hi Goran, > Thanks again for your response. > when using the -ir option I managed to get my PAR right, but now I'm > worried about the results of not using the RLOC constraints. Is there a > danger that my design wont work properly now ? > Thanks again, Mordehay. > > > G=F6ran Bilski wrote: > > Hi, > > > > There is no way to tell MicroBlaze not to use RLOC. > > You can however tell the ISE tools to ignore RLOCs. > > The map needs the parameter -ir > > > > G=F6ran > > > > > > > > <me_2003@walla.co.il> wrote in message > > news:1162829316.487307.248680@m73g2000cwd.googlegroups.com... > > Hi Goran, > > > > Is there any way to instruct the platgen not to use RLOC for the > > microblaze? > > It is just that now (after doing what you suggested above) my mapping > > went well but the PAR fails - It says that a certain core (xilinx > > reed-solomon decoder) cannot be placed. I figured out that maybe the > > RLOCs of the microblaze causes this problem (my chip utilization is > > under 50%). > > Thanks in advance, Mordehay. > > > > error snippet from par log file : > > > > -----------------------------------------------------------------------=---------------------------------------------------> > Starting Placer > > > > Phase 1.1 > > ERROR:Place:346 - The components related to The RPM > > "CORE/RFEC_i/rs_dec_i/rs_docoder_i/rs_dec/dec/sy/nig1/ffo1/r1" can > > not be > > placed in the required relative placement form > > > > The following components are part of this structure: > > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N207 > > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19412 > > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19411 > > SLICEL CORE/RFEC_i/rs_dec_i/rs_docoder_i/N19409 > > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N208 > > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N204 > > SLICEM CORE/RFEC_i/rs_dec_i/rs_docoder_i/N202 > > > > The reason for this issue is the following: > > This logic may be too large or of too irregular shape to fit on the > > device. > > -----------------------------------------------------------------------=---------------------------------------------------> > > > > > > > > > G=F6ran Bilski wrote: > > > Hi, > > > > > > The problem is that the two microblazes have the exact same name. > > > MicroBlaze is a RLOC block which requires a unique name. > > > > > > In this case, I think you need to create two EDK designs which are mo=re> > > or > > > less the same except for the instance name of MicroBlaze > > > or you can also create two microblaze in one EDK design. > > > > > > G=F6ran > > > > > > <me_2003@walla.co.il> wrote in message > > > news:1162808786.323369.313200@h48g2000cwc.googlegroups.com... > > > > Hi, > > > > I have a design in which I need to instantiate two microblaze system > > > > instances (the same microblaze system in two places). > > > > I'm doing it by the following way: > > > > 1) I've created a system containing a single microblaze (in EDK) > > > > 2) I've instantiated it in my hdl code in two different places. > > > > 3) Then I merged the two bmm files into a single bmm file which loo=ks> > > > like this: > > > > > > > > ///////////////////////////////////////////////////////////////////=////////////> > > > // > > > > // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > > > // > > > > ///////////////////////////////////////////////////////////////////=////////////> > > > > > > > ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > > > BUS_BLOCK > > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > > > CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > > > END_BUS_BLOCK; > > > > END_ADDRESS_BLOCK; > > > > > > > > ///////////////////////////////////////////////////////////////////=////////////> > > > // > > > > // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). > > > > // > > > > ///////////////////////////////////////////////////////////////////=////////////> > > > > > > > ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] > > > > BUS_BLOCK > > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; > > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; > > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; > > > > CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; > > > > END_BUS_BLOCK; > > > > END_ADDRESS_BLOCK; > > > > > > > > 4) I synthesize my design using synplify 8.1 > > > > 5) I call the following script (for translate and map) > > > > > > > > ngdbuild -a -p XC4VLX80-FF1148-10 -bm > > > > /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tm=ac.bmm> > > > -sd ../../../../syn/syn_v4/edf > > > > -uc ../../bs_lx80.ucf bs rev1/bs.ngd; > > > > > > > > map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b > > > > rev1/bs.ngd rev1/bs.pcf; > > > > > > > > The ngdbuild goes well but the mapping process has lots of errors (=it> > > > seems that the mapper tries to place the two microblaze instances on > > > > top of each other) > > > > part of the map log file (.mrp) is attached > > > > Can you please advise ? > > > > Thanks in advance, Mordehay. > > > > > > > > Snippet of the map report file (originaly conatins 465 errors): > > > > > > > > Release 7.1.03i Map H.41 > > > > Xilinx Mapping Report File for Design 'bs' > > > > > > > > Design Information > > > > ------------------ > > > > Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o > > > > rev1/map.ncd -pr > > > > b rev1/bs.ngd rev1/bs.pcf > > > > Target Device : xc4vlx80 > > > > Target Package : ff1148 > > > > Target Speed : -10 > > > > Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ > > > > Mapped Date : Mon Nov 6 11:55:10 2006 > > > > > > > > Design Summary > > > > -------------- > > > > Number of errors : 465 > > > > Number of warnings :3074 > > > > > > > > Section 1 - Errors > > > > ------------------ > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y0) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I31/reg1_Data_Low) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I31/reg1_Data_Low) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y1) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I31/reg1_Data_High) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I31/reg1_Data_High) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y2) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I15/reg1_Data_Low) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I15/reg1_Data_Low) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y3) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I15/reg1_Data_High) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I15/reg1_Data_High) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX1Y0) which require the combination of the following symbo=ls> > > > into a > > > > single SLICE component: > > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_=Data<31>)> > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/Reg1_Mux" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_=Data<31>)> > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) > > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) > > > > There are more than two function generators. Please correct the > > > > design > > > > constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y4) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I30/reg1_Data_Low) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I30/reg1_Data_Low) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX1Y1) which require the combination of the following symbo=ls> > > > into a > > > > single SLICE component: > > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I=/OPB_Data_> > > > Mux_I1/MUX_LUT31" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<3=1>)> > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I=/OPB_Data_> > > > Mux_I1/MUX_LUT31" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<3=1>)> > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_=Data<31>)> > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/Reg2_Mux" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_=Data<31>)> > > > There are more than two function generators. Please correct the > > > > design > > > > constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y5) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I30/reg1_Data_High) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I30/reg1_Data_High) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX1Y2) which require the combination of the following symbo=ls> > > > into a > > > > single SLICE component: > > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_=Data<15>)> > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/Reg1_Mux" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_=Data<15>)> > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write<15= >) > > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write<15= >) > > > > There are more than two function generators. Please correct the > > > > design > > > > constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y6) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I14/reg1_Data_Low) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I14/reg1_Data_Low) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX1Y3) which require the combination of the following symbo=ls> > > > into a > > > > single SLICE component: > > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I=/OPB_Data_> > > > Mux_I1/MUX_LUT15" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<1=5>)> > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I=/OPB_Data_> > > > Mux_I1/MUX_LUT15" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<1=5>)> > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_=Data<15>)> > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I15/Reg2_Mux" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_=Data<15>)> > > > There are more than two function generators. Please correct the > > > > design > > > > constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y7) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I14/reg1_Data_High) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I14/reg1_Data_High) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX1Y4) which require the combination of the following symbo=ls> > > > into a > > > > single SLICE component: > > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal =3D > > > > CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) > > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal =3D > > > > CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) > > > > LUT symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_=Data<30>)> > > > LUT symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I30/Reg1_Mux" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_=Data<30>)> > > > There are more than two function generators. Please correct the > > > > design > > > > constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y8) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I29/reg1_Data_Low) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I29/reg1_Data_Low) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX2Y0) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I31/reg2_Data_Low) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I31/reg2_Data_Low) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > ERROR:Pack:679 - Unable to obey design constraints > > > > (MACRONAME=3Dmicroblaze_0, > > > > RLOC=3DX0Y9) which require the combination of the following symbo=ls> > > > into a > > > > single SLICEM component: > > > > RAMDP symbol > > > > > > > > "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I29/reg1_Data_High) > > > > RAMDP symbol > > > > > > > > "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regi=ster_File_> > > > I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal =3D > > > > > > > > CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Regis=ter_File_I> > > > /Register_File_Bit_I29/reg1_Data_High) > > > > The address signals must match exactly when using both F and G in > > > > RAM mode. > > > > Please correct the design constraints accordingly. > > > > > > > > and it continues like this .... > > > >
