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verilog 2 VHDL translator

Started by Quesito November 28, 2006
Hi all,
I'm looking for a verilog to VHDL translator.
Does anybody can point me for a free tool please?

thanks in advance,
Francesco

Quesito wrote:
> Hi all, > I'm looking for a verilog to VHDL translator. > Does anybody can point me for a free tool please?
emacs? Everybody wants something for free these days... How we supposed to earn a living? Cheers, Jon
Jon Beniston schrieb:

> Quesito wrote: > > Hi all, > > I'm looking for a verilog to VHDL translator. > > Does anybody can point me for a free tool please? > > emacs? > > Everybody wants something for free these days... How we supposed to > earn a living? > > Cheers, > Jon
I have a perl script that does most of the conversion work, but usualy leaves the resuting file needing some editing.I don't know about free though I mean whats it worth ???
Jon I will be happy to have a look at your perl script!

Francesco

jez-smith@hotmail.co.uk wrote:

> Jon Beniston schrieb: > > > Quesito wrote: > > > Hi all, > > > I'm looking for a verilog to VHDL translator. > > > Does anybody can point me for a free tool please? > > > > emacs? > > > > Everybody wants something for free these days... How we supposed to > > earn a living? > > > > Cheers, > > Jon > I have a perl script that does most of the conversion work, but usualy > leaves the resuting file needing some editing.I don't know about free > though I mean whats it worth ???