min propagation delay in xilinx cpld

Peter,

Peter Alfke <peter@xilinx.com> wrote in message news:<3FFD91F8.5C4BA92A@xilinx.com>...
> Guille,
> your source promises a min delay that is 10% of its max delay. You are
> safe in assuming a similar ratio for the CPLD. That means max 10 ns, min
> 1.0 ns.
> This seemingly ridiculously loose specification is the result of many factors:
> Processing tolerances including "down-binning" where the manufacturer
> marks a faster ( and more valuable) part as a slower speed grade,
> because therehappens to be more demand for that grade.
> Then temperature ( cold is faster) and Vcc tolerances ( high is faster).
> Plus additional guardband, since the min parameter is not actually
> tested ( the max value is ), plus a lot of tester guardband if it were tested.
> 
> But 10% is a safe value, as long as you do not retrofit five years from
> now, when you might get surprised by a much faster part...
> 
> It is always safer to design in sucha way that min delays values do not matter.

Yes -- in fact the design _is_ done in such a way that it doesn't depend
on the min delays. I just need to work them out in order to document them
on the system's datasheet.

The 10% rule is OK although while we're at it I may as well take zero ns
for the propagation delay. As you say:

> You can always be sure that the min delay will never be less than zero.

Sure! ;)

> Peter Alfke, Xilinx

Thanks for your helpful answer!

Regards,
Guillermo Rodriguez

guille wrote:
> Uh? That's the first time I heard about timing changing due to age
>
And hopefully you will nrvrt hear this kind of nonsense again.
Different from humans, silicon does not get slower with age, or more
tired. Doesn't get any smarter either. ;-) 
 It just stays the way it is, unless somebody overstresses it (mainly in
the I/O)
Peter Alfke, Xilinx
>

The timing comment was general and I did not say slower. Timing changes with
process, temperature, voltage, humidity, packaging etc. The variances might
be small but you are unlikely to get exactly the same timing between 2
device on 2 boards even if they come from the same batch. If you are in the
area of race conditions then all these factors can make one board work and
another not. As usual check the minimum and maximum timings and ensure that
there are sufficient timing margin. If 10% of CPLD maximum works as a
reliable minimum then timing stability can be assessed however the source
device variance also needs to be checked.

John Adair
Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.



"Peter Alfke" <peter@xilinx.com> wrote in message
news:4002D330.6747ABB4@xilinx.com...
>
>
> guille wrote:
> > Uh? That's the first time I heard about timing changing due to age
> >
> And hopefully you will nrvrt hear this kind of nonsense again.
> Different from humans, silicon does not get slower with age, or more
> tired. Doesn't get any smarter either. ;-)
>  It just stays the way it is, unless somebody overstresses it (mainly in
> the I/O)
> Peter Alfke, Xilinx
> >