Verilog Benchmarks for FPGA research

Started by news January 8, 2004
As it is my first time to comp.arch.fpga I will briefly mention that 
I'm working on a front-end verilog compiler that targets both academic 
FPGAs as well as Altera's Quartus Flow.  

I am at a point where I need benchmarks.  I have searched the web as well 
as, but I need more.   The main aspect of the benchmark 
which would be most useful is both size (actual transistor size) and the 
existance of multipliers in the design.

Peter Jamieson
PhD. Candidate at the University of Toronto