Strange JTAG TCK problems with Spartan XC3S400

Addressed to the XILINX insiders:

I have made me myself a small pcb which is basically a replica of the simple
Xilinx JTAG download cable. This JTAG interface works well with Xilinx CPLDs
and also with Altera FPGAs and CPLDs (after some pin mapping on the printer
port side, of course, making it look like a Byteblaster cable to the Altera
tools).

However, if I try to program a Spartan XC3S400 on a board coming from

http://www.siphec.com

the JTAG id is read wrong and programming fails. After some experiments and
talking to the developers at Siphec it turned out that a resistor in the
order of 560 Ohms to ground on the TCK line will solve the problem. At the
first glance one might think that this resistor works as kind of cable
termination reducing reflections on the clock line.

The strange thing is: The positive effect of the resistor takes place ONLY
if the resistor is mounted close to the 74HC125, i.e. BEFORE the JTAG cable
connection to the aimed board. If the resistor is soldered to the aimed
board near the fpga(where it could work as a termination)  programming will
fail as well. This all looks very mysterious to me!

Is there some special TCK conditioning necessary for the Spartans that I am
not aware of and that lets them behave different to other fpgas/cplds ??

TIA for your help
Ulrich Bangert

Ulrich Bangert wrote:
> Addressed to the XILINX insiders:
>
> I have made me myself a small pcb which is basically a replica of the simple
> Xilinx JTAG download cable. This JTAG interface works well with Xilinx CPLDs
> and also with Altera FPGAs and CPLDs (after some pin mapping on the printer
> port side, of course, making it look like a Byteblaster cable to the Altera
> tools).
>
> However, if I try to program a Spartan XC3S400 on a board coming from
>
> http://www.siphec.com
>
> the JTAG id is read wrong and programming fails. After some experiments and
> talking to the developers at Siphec it turned out that a resistor in the
> order of 560 Ohms to ground on the TCK line will solve the problem. At the
> first glance one might think that this resistor works as kind of cable
> termination reducing reflections on the clock line.
>
> The strange thing is: The positive effect of the resistor takes place ONLY
> if the resistor is mounted close to the 74HC125, i.e. BEFORE the JTAG cable
> connection to the aimed board. If the resistor is soldered to the aimed
> board near the fpga(where it could work as a termination)  programming will
> fail as well. This all looks very mysterious to me!
>
> Is there some special TCK conditioning necessary for the Spartans that I am
> not aware of and that lets them behave different to other fpgas/cplds ??
>
> TIA for your help
> Ulrich Bangert

There is a schematic on the Xilinx web site for their Parallel-III
programming cable.  This cable is used to program both CPLDs and FPGAs.
 Notice that there are _no_ pull down resistors.  However, there are
capacitors from the outputs of the HC125s to ground.
  schematic - http://www.xilinx.com/support/programr/files/0380507.pdf
HTH
-Dave Pollum