RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?

Is it just me or is the documentation for the RocketIO (MGT) for the
Xilinx Virtex4 very bad?  I'm trying to find duty cycle requirements
for the MGT clock.  Is it OK to use a clock with a 40% duty cycle?

Also, if anyone can point me to some better RocketIO (MGT)
documentation for the hardware guys I'd appreciate it.  I already have
ug076.

Thanks,
Dale

Dale wrote:
> Is it just me or is the documentation for the RocketIO (MGT) for the
> Xilinx Virtex4 very bad?  I'm trying to find duty cycle requirements
> for the MGT clock.  Is it OK to use a clock with a 40% duty cycle?
> 
> Also, if anyone can point me to some better RocketIO (MGT)
> documentation for the hardware guys I'd appreciate it.  I already have
> ug076.

There is no duty cycle specification for the RocketIO reference
clock as this only feeds the PLL with the MGT.  The important
characteristics for this source are the jitter specifications.
A 40/60 duty cycle would be fine so long as the jitter of the
edges meets the requirements.

Ed McGettigan
--
Xilinx Inc.

Dale,

What are you trying to do with MGTs? I have recently got two V4 FPGAs (one 
CES2, another CES4) streaming to each other at 3.36 Gbps using simplex 
Aurora cores. The learning curve wasn't easy, but in the end everything 
worked as a charm!

/Mikhail


"Dale" <dale.prather@gmail.com> wrote in message 
news:1168541088.454548.159100@i39g2000hsf.googlegroups.com...
> Is it just me or is the documentation for the RocketIO (MGT) for the
> Xilinx Virtex4 very bad?  I'm trying to find duty cycle requirements
> for the MGT clock.  Is it OK to use a clock with a 40% duty cycle?
>
> Also, if anyone can point me to some better RocketIO (MGT)
> documentation for the hardware guys I'd appreciate it.  I already have
> ug076.
>
> Thanks,
> Dale
>