DDR FPGA Design

On 6 Feb., 05:43, "Tommy Thorn" <tommy.th...@gmail.com> wrote:

Tommy,

> Having read through a bunch of Xilinx DDR app notes, I'm confused. It
> seems that the only way to use DDR with a Spartan-3 at high speed is
> to deal with a carefully constructed LUT-delay chain, subject to
> manual routing and other nightmares. Other competing products, such as

I've done my own DDR controller (targeted at the Spartan3E-Starter
Kit) some
months ago and it wasn't that hard.  It interfaces 16 Bit, 130MHz DDR
to a 64 bit
wishbone bus at 65 MHz. [1]

It's not very felxible, and in retrospective i should have done an
asyncronous
design where the wishbone bus can be arbitraty clocked...
But.. hey, it was one of my very first VHDL projects.

  j.


[1] https://roulette.das-labor.org/trac/wiki/wb_ddr

"Tommy Thorn" <tommy.thorn@gmail.com> wrote:

>Having read through a bunch of Xilinx DDR app notes, I'm confused. It
>seems that the only way to use DDR with a Spartan-3 at high speed is
>to deal with a carefully constructed LUT-delay chain, subject to
>manual routing and other nightmares. Other competing products, such as

I wouldn't go that route. It will require regular delay calibrations
because of temperature changes and aging. Worse, it will make your
design behave different in every product you make because each fpga
will have different delays. An FPGA which is just within spec may
trigger a bug in your design! The best way in a Spartan3 and similar
devices is using a shifted clock to feed the IOB flipflops.

>the Cyclone I & II have programmable delays in some of the IOBs,
>making centering on the DQS trivial in comparison.

You can use the IOB delay in the Spartan3 to center the DQS, but the
routing of the DQS clock to the IOB flipflops is very restricted and
not (well) documented. You'll need to design the FPGA first and then
the PCB. Also, the timing is more critical then when using a shifted
clock! I posted some messages in this newsgroup on this topic before.

Expect a Spartan3 DDR design to run at 100MHz in speedgrade 4 and at
125MHz in a speedgrade 5 device.


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